公开(公告)号：SG11201705347RA

公开(公告)日：2017-08-30

申请号：SG11201705347R

申请日：2016-02-03

Applicant: QUALCOMM INC

Inventor： KIDWELL DONALD WILLIAM JR ,  SHENOY RAVINDRA ,  ERTURK METE ,  ROUHANA LAYAL

IPC: H01F17/00 ,  H01L23/498 ,  H01L21/48

Abstract: An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

公开(公告)号：WO2016100829A3

公开(公告)日：2016-08-25

申请号：PCT/US2015066698

申请日：2015-12-18

Applicant: QUALCOMM INC

Inventor： SONG YOUNG KYU ,  ROUHANA LAYAL ,  HWANG KYU-PYUNG ,  BCHIR OMAR JAMES

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H05K3/12 ,  H05K3/34

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/167 ,  H05K1/181 ,  H05K3/1258 ,  H05K3/321 ,  H05K3/3442 ,  H05K3/4697 ,  H05K2201/0792 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/0545 ,  Y02P70/611

Abstract: Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.

Abstract translation: 提供了用于控制电容器的等效串联电阻（ESR）的方法和装置。 示例性装置包括具有接地侧的基板，安装在基板的接地侧上并具有ESR和端子的电容器，耦合到端子的电阻图案以及耦合到电阻图案的多个通孔。 电阻模式被配置为控制ESR。 电阻图案可以由电阻浆料形成。 电阻图案可以形成为具有大致45度至基本上135度的弧度的大致半圆形状。 电容器可以是表面贴装器件。 电阻图案可以形成为陆侧电容器安装垫，通孔或两者的形状。