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    Vdmos transistor
    3.
    发明专利
    Vdmos transistor 有权
    VDMOS晶体管

    公开(公告)号：JPH11274495A

    公开(公告)日：1999-10-08

    申请号：JP1337099

    申请日：1999-01-21

    Applicant: St Microelectronics Srl ,  エスティーマイクロエレクトロニクスエス.アール.エル.

    Inventor： CHIOZZI GIORGIO ,  ANDREINI ANTONIO

    IPC: H01L29/06 ,  H01L21/76 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78 ,  H02M1/00

    CPC classification number: H01L27/0251 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7811

    Abstract: PROBLEM TO BE SOLVED: To avoide an overvoltage between a source and a gate in which a gate dielectric of VDMOS(vertical double diffusion MOS) transistors formed in an active region of an integrated circuit which is junctioned and isolated may be damaged or broken.
    SOLUTION: MOS transistors are formed in an active region 13, and the gate electrode is connected to a gate electrode 17 of VDMOS transistors and a source region of the MOS transistors is made common to a source region 9 of the VDMOS trasistors, and drain regions 30, 31 of the MOS transistors are coupled to a junction and isolation region 14. A threshold voltage of the MOS transistors is lower than a breakdown voltage of a gate dielectric of the VDMOS transistors, and the MOS transistors act as a voltage limitter.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：为了避免源极和栅极之间的过电压，其中形成在结合和隔离的集成电路的有源区中的VDMOS（垂直双重扩散MOS）晶体管的栅极电介质可能被损坏或破坏。 解决方案：MOS晶体管形成在有源区13中，栅电极连接到VDMOS晶体管的栅电极17，并且MOS晶体管的源极区域与VDMOS晶体管的源极区9相同，漏区 30,31的MOS晶体管耦合到结和隔离区14.MOS晶体管的阈值电压低于VDMOS晶体管的栅极电介质的击穿电压，并且MOS晶体管用作电压限制器。

    5.
    发明专利
    未知

    公开(公告)号：DE3788438T2

    公开(公告)日：1994-04-07

    申请号：DE3788438

    申请日：1987-01-21

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ANDREINI ANTONIO

    IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L21/82

    Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted

    6.
    发明专利
    未知

    公开(公告)号：DE3788438D1

    公开(公告)日：1994-01-27

    申请号：DE3788438

    申请日：1987-01-21

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ANDREINI ANTONIO

    IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L21/82

    Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted

    9.
    发明专利
    未知

    公开(公告)号：DE3778961D1

    公开(公告)日：1992-06-17

    申请号：DE3778961

    申请日：1987-02-23

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CONTIERO CLAUDIO ,  ANDREINI ANTONIO ,  GALBIATI PAOLA

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L29/10

    Abstract: Described is an improved fabrication process for vertical DMOS cells contemplating the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, allowing also to form the source region. Opening of the relative contact is also effected by self alignment technique, further simplifying the process.

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