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    MOS TECHNIQUE POWER DEVICE
    1.
    发明专利
    MOS TECHNIQUE POWER DEVICE 失效

    公开(公告)号：JPH09298301A

    公开(公告)日：1997-11-18

    申请号：JP28872996

    申请日：1996-10-30

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

    IPC: H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a power device with a higher integration scale than a conventional MOS technique power device. SOLUTION: This device is provided with a conductive insulating gate layer covering a first conductivity type semiconductor layer and a plurality of basic function unit. Each basic function unit contains a slim window formed on an insulating gate layer 9 extending on a slim base body 3. The first conductivity type source regions 60 not doped with impurities of the main parts 40 are alternately positioned in each slim base body 3. Further, a side wall spacer of an insulating material is formed along a longitudinally directed edge of each slim window so as to seal an edge of each slim window. A source metal layer is brought into contact with each slim main body region and each source region through each main body region.

    MOS TECHNOLOGY POWER DEVICE
    2.
    发明专利
    MOS TECHNOLOGY POWER DEVICE 失效

    公开(公告)号：JPH09252115A

    公开(公告)日：1997-09-22

    申请号：JP28875896

    申请日：1996-10-30

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： MAGRI ANGELO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To make the contact of source metal layers and main body areas satisfactory even if scaled down to the limit of photolithography and to realize high integration. SOLUTION: Respective basic function unit contain second conductive long main body areas 3 being parallel bars which are formed in a semiconductor material layer and are detached by the distance (d). Main body parts 40 to which first conductive impurities are not given and first conductive source areas 60 are mutually positioned in the respective long main body areas 3. Openings 11 are provided for dielectric layers 9 sealing the conductive layers to be grown to gates along the center parts of the long main body areas 3. The metal layers constituting a source electrode are brought into contact with the source areas 60 and the main body parts 40.

    POWER DEVICE INTEGRATED STRUCTURE
    5.
    发明专利
    POWER DEVICE INTEGRATED STRUCTURE 失效

    公开(公告)号：JPH0864811A

    公开(公告)日：1996-03-08

    申请号：JP19326495

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/78 ,  H01L29/739

    Abstract: PROBLEM TO BE SOLVED: To prevent trigger-ons of a parasitic thyristor and to reduce static losses by allowing the sum of the common base current gain of a first bipolar junction type transistor and the current gain of a second bipolar junction type transistor to be 1 or greater. SOLUTION: A source region 11, a channel region 7, and an n-type layer 3 constitute a power MOSFET. The source region 11, a main body region 2, and the n-type layer 3 form the first npn bipolar junction type transistor T1. Furthermore, a substrate 5, the n-type layer 3, and the main body region constitute the second pnp bipolar junction type transistor T2. The sum of base current gains αn and αp of the npn bipolar junction type transistor T1 and pnp bipolar junction type transistor T2 are set so as to be 1 or greater. When the power MOSFET is driven on, both transistors are biased in the forward direction, resulting in αn +αp

    MANUFACTURE OF HIGH DENSE MOS TYPE ELECTRIC POWER DEVICE ANDHIGH DENSE TYPE ELECTRIC POWER DEVICE MANUFACTURED BY ITS METHOD
    6.
    发明专利
    MANUFACTURE OF HIGH DENSE MOS TYPE ELECTRIC POWER DEVICE ANDHIGH DENSE TYPE ELECTRIC POWER DEVICE MANUFACTURED BY ITS METHOD 失效

    公开(公告)号：JPH0897168A

    公开(公告)日：1996-04-12

    申请号：JP16869395

    申请日：1995-07-04

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of highly integrated MOS power device. SOLUTION: Insulating gate layers 8 and insulating layers 11 are formed on a semiconductor layer 2, next to a plurality of slender windows having long edges 17 and short edges sectioning respectively exposed surface fine strips 16 are formed by selectively removing layers 8 and 11. Then the slender windows are implanted with a first dopant vertically thereto and perpendicularly to the layer 2 so as to be symmetrically tilted at the surface of the layer 2 making an angle. These angles depending upon the gross thickness of the layers 8 and 11 for preventing the first dopant from being implanted into the central fine strips of the fine strips 16 to form the pairs of source regions 6 extending along the edges 17 of respective windows, also separated by the central fine strips further symmetrically tilted making another angle to be implanted with a second dopant to form respective regions with two channel regions 5, extending to the under side of the long edges of respective windows finally implanted with a third dopant to form the regions aligned with the edges 17 of the windows using the layers 11 as masks.

    MOS TECHNIQUE HIGH-SPEED ELECTRIC POWER DEVICE OF INTEGRATEDSTRUCTURE AND ITS PREPARATION
    7.
    发明专利
    MOS TECHNIQUE HIGH-SPEED ELECTRIC POWER DEVICE OF INTEGRATEDSTRUCTURE AND ITS PREPARATION 失效

    公开(公告)号：JPH0846200A

    公开(公告)日：1996-02-16

    申请号：JP17871495

    申请日：1995-07-14

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide an MOS technology power device having integrated circuit in which the series resistance of gate can be decreased without increasing the number of gate metal finger parts. SOLUTION: The MOS technology power device of integrated structure comprises a plurality of functional units of basic component formed in a lightly doped first conductivity type semiconductor layer 1 wherein the functional unit has a second conductivity type channel region 6 coated with a conductive insulation gate layer 8 including a polysilicon layer 5. The conductive insulation gate layer 8 has resistivity significantly lower than that of the polysilicon layer 5 superposed by a highly conductive layer 9. Since a resistance introduced by the polysilicon layer 5 is shunted by a resistance introduced by the highly conductive layer 9, total resistivity of the conductive insulation gate layer 8 is decreased.

    MOS-TECHNOLOGY POWER-DEVICE CHIP AND PACKAGE ASSEMBLY
    8.
    发明专利
    MOS-TECHNOLOGY POWER-DEVICE CHIP AND PACKAGE ASSEMBLY 失效

    公开(公告)号：JPH08213614A

    公开(公告)日：1996-08-20

    申请号：JP19759695

    申请日：1995-08-02

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L21/60 ,  H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To reduce a parasitic resistance value and inductance of wire and pin by separating units comprising a plurality of function units with such a region of a semiconductor layer as no function unit is formed. SOLUTION: A semiconductor material layer 5 is selectively coated with an insulated gate layer 11 extending on a first doped region 7, and the gate layer 11 is made to contact gate metal meshes 101 and 102 connected to at least one gate metal pad, while surrounding a source metal plate 100. By connecting the gate metal pad to each pin P8 of a package with each bonding wire W8, all MOSFET units among all the MOSEFT units are connected in parallel. Thus, the maximum current capacity of the power device can be re- established, while each source electrode pin can be electrically speared according to individual purposes, resulting in significantly improved freedom in design.

    MANUFACTURE OF MOS TYPE ELECTRIC POWER DEVICE
    9.
    发明专利
    MANUFACTURE OF MOS TYPE ELECTRIC POWER DEVICE 失效

    公开(公告)号：JPH0817848A

    公开(公告)日：1996-01-19

    申请号：JP15598295

    申请日：1995-06-22

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739

    Abstract: PURPOSE: To ignore the base series resistance of a parasitic perpendicular bipolar transistor by adjusting an ion implantation energy so that the peak of the dopant concentration of a heavily doped part of a body region is located on the lower side of a source region than the surface of a semiconductor layer. CONSTITUTION: With an insulation gate layer 10 on the surface of a semiconductor layer 3 as a mask, a first impurity is ion-implanted with an energy in a specific thickness from the surface of the semiconductor layer 3 and is thermally diffused, thus forming a body region 2 consisting of a first greatly doped part 5 that is nearly aligned to both edges of the insulation layer 10 and a horizontal diffusion part 6 at the lower side of the insulation layer 10. The second impurity is ion-implanted selectively into the body region 2 in a pair, thus forming an annular source 7 that is aligned to both edges of the insulation layer 10, thus forming the greatly doped part 5 of the first impurity so that it is located at the lower side of the annular source region 7 and ignoring the base series resistance of a parasitic perpendicular bipolar transistor.

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