公开(公告)号：JPH09167948A

公开(公告)日：1997-06-24

申请号：JP12963996

申请日：1996-05-24

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： CANTONE GIUSEPPE ,  NOVELLI ALDO

IPC: H03K5/1532 ,  H03K5/1252

Abstract: PROBLEM TO BE SOLVED: To provide a pulse generator provided with one input terminal and with two output terminals from which a pulse is generated respectively depending on an edge of a different type received by the input terminal. SOLUTION: This pulse generator has two separate logic circuit blocks FF1, FF2 of a sequential type and then the production of a pulse at each of two output terminals OR, OS is independently of each other. Thus, the characteristic of each pulse is easily controlled. Furthermore, when the two blocks are interconnected by a proper and simple logic circuit network consisting of G3, G4, it is possible to provide a condition in a simple mode with a degree of freedom between pulses at the two output terminals in the case of producing the pulses.

公开(公告)号：DE69530288D1

公开(公告)日：2003-05-15

申请号：DE69530288

申请日：1995-05-31

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： CANTONE GIUSEPPE ,  NOVELLI ALDO

IPC: H03K5/1532 ,  H03K5/1252 ,  H03K5/01 ,  H03K5/153

Abstract: The present invention relates primarily to a pulse generator (GEN) having an input (ID) and two outputs (OR,OS) at which to generate respectively a pulse in relation to a edge of a different type at input. The generator provides two distinct logic circuit blocks of the sequential type hence mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks (G3,G4) it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

公开(公告)号：DE69125648D1

公开(公告)日：1997-05-22

申请号：DE69125648

申请日：1991-05-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BAIOCCHI ANTONELLA ,  ALZATI ANGELO ,  NOVELLI ALDO

IPC: H03K5/1254 ,  H03K5/1252 ,  H03K5/01

Abstract: A spike filtering circuit for a logic signal comprises a signal trasfer circuit formed by a first transfer (TG1) gate followed by a pair of inverters (INV1,INV2), functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate (TG2) connected between the output terminal and the input node of the first of said two inverters (INV1). The two transfer gates (TG1,TG2) are driven in phase opposition to each other by means of a pair of control signals (CK,CK) in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate (XOR) having two inputs connected to the output terminal of the circuit directly and through a delay network (d), respectively. Through an output node of the exlusive-OR gate (XOR) is produced a first control signal (2) from which the pair of control signals (CK,CK) in phase opposition to each other are derived by means of inverting stages. The delay network (d) introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate (TG1) is momentarily disabled and said second transfer gate (TG2) is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may have been generated by said transition of the logic signal. By employing a NAND gate (NAND) and an inverter (INV3) connected in cascade to the output of said exclusive-OR gate (XOR), the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.

公开(公告)号：IT1236879B

公开(公告)日：1993-04-26

申请号：IT2247489

申请日：1989-11-22

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： ALZATI ANGELO ,  NOVELLI ALDO

IPC: H03F3/45 ,  H03K5/08 ,  H03K5/24 ,  H03F

Abstract: An electronic comparator circuit (1), of a type which comprises a first, differential stage (2) input circuit portion provided with a differential pair of bipolar transistors (T2,T3) forming respective outputs of thee input portion (2), is further provided with an output stage (3) comprising a first pair of MOS transistors (M1,M2), with gate electrodes (G1,G2) in common, respectively connected on the one side to said outputs (C2,C3) and on the other side to a positive supply pole (Vc) via a current mirror circuit, and a second pair of MOS transistors (M5,M6), with gate electrodes (G5,G6) in common, connected between said outputs (C2,C3) and ground. A drain electrode (D2) of the first pair of MOS transistors (M1,M2) forms an output (OUT) for the comparator (1), the latter having shown itself to be specially fast during the switch phase and combining the advantages of bipolar technology circuits and of those in the CMOS technology.

公开(公告)号：DE69125648T2

公开(公告)日：1997-09-18

申请号：DE69125648

申请日：1991-05-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BAIOCCHI ANTONELLA ,  ALZATI ANGELO ,  NOVELLI ALDO

IPC: H03K5/1254 ,  H03K5/1252 ,  H03K5/01

Abstract: A spike filtering circuit for a logic signal comprises a signal trasfer circuit formed by a first transfer (TG1) gate followed by a pair of inverters (INV1,INV2), functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate (TG2) connected between the output terminal and the input node of the first of said two inverters (INV1). The two transfer gates (TG1,TG2) are driven in phase opposition to each other by means of a pair of control signals (CK,CK) in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate (XOR) having two inputs connected to the output terminal of the circuit directly and through a delay network (d), respectively. Through an output node of the exlusive-OR gate (XOR) is produced a first control signal (2) from which the pair of control signals (CK,CK) in phase opposition to each other are derived by means of inverting stages. The delay network (d) introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate (TG1) is momentarily disabled and said second transfer gate (TG2) is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may have been generated by said transition of the logic signal. By employing a NAND gate (NAND) and an inverter (INV3) connected in cascade to the output of said exclusive-OR gate (XOR), the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.

公开(公告)号：DE69030427D1

公开(公告)日：1997-05-15

申请号：DE69030427

申请日：1990-10-17

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GOLA ALBERTO ,  ALZATI ANGELO ,  NOVELLI ALDO

IPC: H03F3/45 ,  H03K5/24 ,  H03K5/08

Abstract: An electronic comparator circuit (1), of a type which comprises a first, differential stage (2) input circuit portion provided with a differential pair of bipolar transistors (T2,T3) forming respective outputs of thee input portion (2), is further provided with an output stage (3) comprising a first pair of MOS transistors (M1,M2), with gate electrodes (G1,G2) in common, respectively connected on the one side to said outputs (C2,C3) and on the other side to a positive supply pole (Vc) via a current mirror circuit, and a second pair of MOS transistors (M5,M6), with gate electrodes (G5,G6) in common, connected between said outputs (C2,C3) and ground. A drain electrode (D2) of the first pair of MOS transistors (M1,M2) forms an output (OUT) for the comparator (1), the latter having shown itself to be specially fast during the switch phase and combining the advantages of bipolar technology circuits and of those in the CMOS technology.

公开(公告)号：IT1243301B

公开(公告)日：1994-05-26

申请号：IT8362290

申请日：1990-05-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BAIOCCHI ANTONELLA ,  ALZATI ANGELO ,  NOVELLI ALDO

IPC: H03K5/1254 ,  H03K5/1252 ,  H03H

Abstract: A spike filtering circuit for a logic signal comprises a signal trasfer circuit formed by a first transfer (TG1) gate followed by a pair of inverters (INV1,INV2), functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate (TG2) connected between the output terminal and the input node of the first of said two inverters (INV1). The two transfer gates (TG1,TG2) are driven in phase opposition to each other by means of a pair of control signals (CK,CK) in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate (XOR) having two inputs connected to the output terminal of the circuit directly and through a delay network (d), respectively. Through an output node of the exlusive-OR gate (XOR) is produced a first control signal (2) from which the pair of control signals (CK,CK) in phase opposition to each other are derived by means of inverting stages. The delay network (d) introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate (TG1) is momentarily disabled and said second transfer gate (TG2) is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may have been generated by said transition of the logic signal. By employing a NAND gate (NAND) and an inverter (INV3) connected in cascade to the output of said exclusive-OR gate (XOR), the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.

公开(公告)号：IT9083622A1

公开(公告)日：1991-11-26

申请号：IT8362290

申请日：1990-05-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： ALZATI ANGELO ,  BAIOCCHI ANTONELLA ,  NOVELLI ALDO

IPC: H03K5/1254 ,  H03H20060101 ,  H03K5/1252

公开(公告)号：DE69030427T2

公开(公告)日：1997-10-16

申请号：DE69030427

申请日：1990-10-17

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GOLA ALBERTO ,  ALZATI ANGELO ,  NOVELLI ALDO

IPC: H03F3/45 ,  H03K5/24 ,  H03K5/08

Abstract: An electronic comparator circuit (1), of a type which comprises a first, differential stage (2) input circuit portion provided with a differential pair of bipolar transistors (T2,T3) forming respective outputs of thee input portion (2), is further provided with an output stage (3) comprising a first pair of MOS transistors (M1,M2), with gate electrodes (G1,G2) in common, respectively connected on the one side to said outputs (C2,C3) and on the other side to a positive supply pole (Vc) via a current mirror circuit, and a second pair of MOS transistors (M5,M6), with gate electrodes (G5,G6) in common, connected between said outputs (C2,C3) and ground. A drain electrode (D2) of the first pair of MOS transistors (M1,M2) forms an output (OUT) for the comparator (1), the latter having shown itself to be specially fast during the switch phase and combining the advantages of bipolar technology circuits and of those in the CMOS technology.

公开(公告)号：IT8922474A1

公开(公告)日：1991-05-22

申请号：IT2247489

申请日：1989-11-22

Applicant: SGS THOMSON MICROELECTRONICS S R L

Inventor： GOLA ALBERTO ,  ALZATI ANGELO ,  NOVELLI ALDO

IPC: H03F3/45 ,  H03F20060101 ,  H03K5/24 ,  H03K5/08