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公开(公告)号：JPH0866089A
公开(公告)日：1996-03-08
申请号：JP16242195
申请日：1995-06-28
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor： GIUSETSUPE DANJIERO , RINARUDO PORUTSUTSUI , MATEO RO PURESUTEI
Abstract: PURPOSE: To improve performance of an applied-voltage fuzzy control process and a usual control system by applying fuzzy control to velocity errors, differen tial coefficient of the velocity error and electric power errors, in order to gener ate the values of a pulse and a voltage which are proper for driving an electric motor. CONSTITUTION: A signal Wref , indicating a reference velocity, is sent to a comparison node 11. The node 11 also receives a signal W indicating a velocity which drives an AC motor. The node 11 is proper for generating a difference Wref -W, i.e., an error EW. The error signal EW is sent to a fuzzy controller 13. At the same time, the error signal EW is sent to a differential circuit 12, which is appropriate for generating a differential coefficient dEW/dt of the error signal EW. The differential coefficient deW/dt is sent to the fuzzy controller 13. A node 16 is appropriate for generating an electric power error signal EP of the fuzzy controller 13.
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公开(公告)号：JPH07141183A
公开(公告)日：1995-06-02
申请号：JP12539794
申请日：1994-06-07
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor： BIAJIYO RUTSUSO , RINARUDO PORUTSUTSUI , KURAUDEIO RUTSUTSUI
Abstract: PURPOSE: To minimize the size of a storage part and to perform an operation at a high calculation speed and at the excellent degree of a resolution by limiting the storage of a belonging relation function corresponding to a point where the value of the degree of the belonging relation of a function is not zero (not null) in a discussion area. CONSTITUTION: Signals from a system 9 to be controlled are converted to fuzzy logic information by a conversion device 2 and then sent to the storage part 5A and the specified storage of only a part of the information is executed there. The size of the storage part 5A is decided in response to the number of the non-zero values of the belonging relation function f (m) at the prescribed point (m) of the discussion area U provided with the maximum number of a non-null value and is far more compact than the size of the storage part obtained by a conventional method. The information stored in the storage part 5A is sent to a buffer part 8 and the restoration of the fuzzy logic information to be used in a calculation part 6 for an appropriate inference operation is implemented there. Thus, while minimizing a required storage capacity for a hardware, the operation is performed at the high calculation speed and at the high degree of the resolution.
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Patent Agency Ranking
公开(公告)号：JPH0651807A
公开(公告)日：1994-02-25
申请号：JP3834693
申请日：1993-02-26
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PAGNI ANDREA , RINARUDO PORUTSUTSUI , JIANGUIDO RITSUOTSUTO
Abstract: PURPOSE: To provide a fuzzy logic electronic controller depending on so called inferring operation in which the prescribed membership function of a logical variable is substantially constituted as a preposition being at least one front part and the rule of 'If...then...', with implication being at least one rear part. CONSTITUTION: This fuzzy logical electronic controller is the kind of including an input part namely a fuzzy fire part 3 provided with plural inputs for an analog signal and digital signal, a central control unit namely a fuzzy controller central part 5 provided behind the input part and provided with plural memories, and an output part namely defuzzy fire 15 connected to the output side of the central control unit and converting the result of inferring operation back to an analog or digital signal.
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公开(公告)号：JPH02189017A
公开(公告)日：1990-07-25
申请号：JP32483989
申请日：1989-12-14
Applicant: SGS THOMSON MICROELECTRONICS
Abstract: PURPOSE: To reduce the storage capacity by connecting the output of each read amplifier, which corresponds to the most significant bit of each value, to a corresponding bit of a related adder and connecting other most significant input bits to all inputs. CONSTITUTION: Each line has a continuous partial product of variable word length. Since the word length is uniform in circuits on the outside of a memory M, it is necessary that bits deleted from words are added at the exit of the memory M to extend the reduced words. When 2's complement expression is selected for the partial product, the most significant bit of the word is repeated several times until the standard word length is obtained. A sum total Nb of required non-zero bits is Nb=b0 T-T /4 where T is the number of coefficients and b0 indicates the precision of the center coefficient. Thus, the number of one-bit cells is reduced by T /4, and it is reduced by 2N×T /4 in the whole of a 2N-line memory.
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公开(公告)号：JPH02189016A
公开(公告)日：1990-07-25
申请号：JP31634489
申请日：1989-12-05
Applicant: SGS THOMSON MICROELECTRONICS
Abstract: PURPOSE: To increase the speed and the performance by driving the address input of a memory cell by a sampled digital signal to be filtered and including a digital value, which is equal to the product of a preliminarily set coefficient and the address of each cell, in the memory cell of each bank. CONSTITUTION: Plural parallel adders are provided which have first and second inputs and outputs and are connected to the first input of an adder, to which parallel outputs of adders 2, 22...24 belong, through delay elements. The second input of each parallel adder is connected in parallel to the output of one of plural memory banks 40, 42, and 44, and memory banks 40, 42...44 have plural addressable memory cells. Address inputs can be driven by the sampled digital signal to be filtered, and each memory cell of each bank has the digital value equal to the product of the preliminarily set coefficient and the address of the cell. Thus, the speed and the performance are increased.
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公开(公告)号：JPH08280039A
公开(公告)日：1996-10-22
申请号：JP24958395
申请日：1995-09-27
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： BUIBUIANA DAARUTO , MATSUSHIMO MANKUUSO , RINARUDO PORUTSUTSUI , JIYANGUIDO RIZOTSUTO
Abstract: PROBLEM TO BE SOLVED: To provide a device for the filtering of video images for effectively performing image filtering following the problems of noise attenuation, space/ time resolution and wide luminance change. SOLUTION: This device is provided with first input terminals PFy and PFuv, second input terminals DFy and CFuv and output terminals corresponding to the output terminal of the device respectively. Further, the device is provided with first and second circuit parts 3 and 4 provided with mutually cascade- connected first filter 5, second filter 6, third filter 8 and forth filter 9 and the first filter 5, the second filter 6 and the third filter 8 are provided with a calculation circuit means for processing a digitized luminance element Y by using a fuzzy theory. Further, the forth filter 9 is provided with the calculation circuit means for processing digitized chrominance elements U and V based on a parameter knr supplied from the second filter 6.
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公开(公告)号：JPH0387974A
公开(公告)日：1991-04-12
申请号：JP14171990
申请日：1990-06-01
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： MISHIEERU TARIERUCHIO , MARIO RABORUUNIA , RINARUDO PORUTSUTSUI , JIANGUIDO RIZOTSUTO
Abstract: PURPOSE: To attain the high speed of calculation by calculating the product of data and a coefficient matrix, and calculating the afterward product of data and the substituted coefficient matrix. CONSTITUTION: Input data and coefficients are supplied through input buses 40 and 41 to registers 35 and 36. Then, two of three connected lines as a set extending from an RAM 34 supplies the coefficients of a substituted matrix through a shift register 38 to a multiplier 32, and supplies data to be transformed to a two-to-one multiplexer register 39. The multiplexer register 39 applies the data from the register 36 or the data from the RAM 34 to a first multiplier 31, and the third line is used for supplying a transformation coefficient from the RAM to the multiplier 31. Moreover, an accumulator 30 executes the accumulation of a second matrix product (first matrix product ×a substituted matrix coefficient), and applies the output of two complements. Thus, the high speed of calculation can be attained.
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