公开(公告)号：FR2969373B1

公开(公告)日：2013-07-19

申请号：FR1060839

申请日：2010-12-20

Applicant: ST MICROELECTRONICS CROLLES 2 ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： HALIMAOUI AOMAR ,  ZUSSY MARC

IPC: H01L21/304

公开(公告)号：FR2969373A1

公开(公告)日：2012-06-22

申请号：FR1060839

申请日：2010-12-20

Applicant: ST MICROELECTRONICS CROLLES 2 ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： HALIMAOUI AOMAR ,  ZUSSY MARC

IPC: H01L21/304

Abstract: Procédé et dispositif correspondant d'assemblage d'une première plaque et d'une deuxième plaque (P1, P2) biseautées à leur périphérie, comprenant une étape d'excavation sur la partie périphérique biseautée (BIS) d'au moins une première face de la première plaque (P1) engendrant un dépôt en bordure de la zone excavée du matériau de la première plaque, et une étape de collage de la première face et d'une deuxième face de la deuxième plaque.

公开(公告)号：WO2006024721A2

公开(公告)日：2006-03-09

申请号：PCT/FR2005001771

申请日：2005-07-08

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  LAURENT JEAN-YVES ,  SALOT RAPHAEL ,  MARSACQ DIDIER ,  ZUSSY MARC

Inventor： LAURENT JEAN-YVES ,  SALOT RAPHAEL ,  MARSACQ DIDIER ,  ZUSSY MARC

IPC: H01M10/04 ,  H01M4/04 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/0585 ,  H01M10/36

CPC classification number: H01M10/0585 ,  H01M2/0257 ,  H01M4/0421 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/052 ,  H01M10/0562 ,  Y10T29/49115

Abstract: The invention relates to a microbattery comprising through-connections and to the production method thereof. The inventive microbattery comprises a support (1) having a front face (2) and a rear face (3) and first (4) and second (5) current collectors which are disposed on the front face (2) of the support (1). A stack comprising a cathode (8) and an anode (6) which are separated by an electrolyte (7) is disposed on the current collectors (4 and 5). The anode (6) and the cathode (8) are in contact with the first (4) and second (5) current collectors respectively. The aforementioned stack is covered with a protective layer (9). In addition, the microbattery comprises connections (10) which pass through the support (1) from the front face (2) to the rear face (3) thereof and which are in contact with the first (4) and second (5) current collectors. The stack preferably covers essentially all of the front face (2) of the support (1). The invention also relates to a method of producing the microbattery, which comprises: the etching of cavities in the front face (2) of the support (1), said cavities having a depth less than the thickness of the support (1); the filling of the cavities with a conductive material; and the removal of a layer of the rear face (3) from the support (1), in order to reveal the conductive material contained in the cavities.

Abstract translation: 本发明涉及一种包括通孔连接的微电池及其制造方法。 本发明的微电池包括具有前表面（2）和后表面（3）的支撑件（1）和设置在支撑件（1）的前表面（2）上的第一（4）和第二（5）集电器 ）。 包括由电解质（7）分离的阴极（8）和阳极（6）的堆叠设置在集流器（4和5）上。 阳极（6）和阴极（8）分别与第一集电体（4）和第二集电体（5）接触。 上述叠层被保护层（9）覆盖。 此外，微电池包括从前表面（2）穿过支撑件（1）到其后表面（3）的连接件（10），它们与第一（4）和第二（5）电流接触 收藏家。 堆叠优选地覆盖支撑件（1）的基本上所有的前表面（2）。 本发明还涉及一种生产微电池的方法，其包括：蚀刻支撑体（1）的前表面（2）中的空腔，所述空腔的深度小于支撑件（1）的厚度; 用导电材料填充空腔; 以及从支撑件（1）去除后表面（3）的层，以便露出包含在空腔中的导电材料。

公开(公告)号：WO2006043000A3

公开(公告)日：2006-12-21

申请号：PCT/FR2005050863

申请日：2005-10-18

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  KOSTRZEWA MAREK ,  DI CIOCCIO LEA ,  ZUSSY MARC

Inventor： KOSTRZEWA MAREK ,  DI CIOCCIO LEA ,  ZUSSY MARC

IPC: H01L21/68 ,  H01L21/00

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/568 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/29 ,  H01L24/96 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01032

Abstract: The invention relates to a method for transferring at least one micrometer or millimeter sized object to a reception substrate by means of a handle. The inventive method consists in fixing a polymer handle to said object in such a way that a deformable structure consisting of the superimposed handle and object is obtainable, in preparing the surface of the object face which is opposite to the handle for the adhesion thereof to the reception substrate face, in bringing said object face into contact with said reception substrate face, adhering it thereto after the deformation at least of the handle and in removing the polymer handle.

Abstract translation: 本发明涉及一种借助于手柄将至少一个微米或毫米大小的物体转移到接收基板的方法。 本发明的方法在于将聚合物手柄固定到所述物体上，使得可以获得由叠加的手柄和物体组成的可变形结构，在制备物体表面的与手柄相对的表面以便粘附到手柄和物体上 在使所述物体表面与所述接收基板表面接触时，在所述手柄的至少一部分变形并且在移除所述聚合物手柄之后将所述物体表面粘附到其上。

公开(公告)号：WO03032383A3

公开(公告)日：2003-10-09

申请号：PCT/FR0203408

申请日：2002-10-07

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ASPAR BERNARD ,  ZUSSY MARC ,  CLERC JEAN-FREDERIC

Inventor： ASPAR BERNARD ,  ZUSSY MARC ,  CLERC JEAN-FREDERIC

IPC: G02F1/1333 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/318 ,  H01L21/762 ,  H01L21/77 ,  H01L21/84

CPC classification number: H01L27/1266 ,  G02F1/1333 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76256 ,  H01L27/1214 ,  H01L2221/68368

Abstract: The invention concerns a method for making a thin layer comprising components or circuits, characterized in that it comprises the following steps: a) forming on a glass substrate a boundary layer; b) producing, on the boundary layer, a thin layer including all or part of at least a component and/or circuit; c) eliminating or thinning the glass substrate.

Abstract translation: 本发明涉及制造包括部件或电路的薄层的方法，其特征在于其包括以下步骤：a）在玻璃衬底上形成边界层; b）在边界层上产生包括至少一个部件和/或电路的全部或部分的薄层; c）消除或减薄玻璃基板。

公开(公告)号：WO2006037933A3

公开(公告)日：2006-06-01

申请号：PCT/FR2005050825

申请日：2005-10-06

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  MORICEAU HUBERT ,  MORALES CHRISTOPHE ,  ZUSSY MARC ,  DECHAMP JEROME

Inventor： MORICEAU HUBERT ,  MORALES CHRISTOPHE ,  ZUSSY MARC ,  DECHAMP JEROME

IPC: H01L21/762

CPC classification number: H01L21/76251 ,  H01L21/7624 ,  H01L21/76254 ,  H01L21/76259

Abstract: The invention concerns a method for producing a semiconductor structure, on a semiconductor substrate whereof one surface has a topology, said method comprising the following steps: a) forming a first layer (24) in a first insulating material on said surface, b) forming a second layer in a second insulating material (28), less dense than the first insulating material, of thickness ranging between 2.5 and 3.5 p, c) planarizing the assembly.

Abstract translation: 本发明涉及在半导体衬底上制造半导体结构的方法，其中一个表面具有拓扑结构，所述方法包括以下步骤：a）在所述表面上形成第一绝缘材料中的第一层（24），b）形成 在第二绝缘材料（28）中的第二层，其密度小于第一绝缘材料，厚度范围在2.5和3.5p之间，c）平坦化组件。

公开(公告)号：WO2004057667A3

公开(公告)日：2004-08-12

申请号：PCT/FR0350188

申请日：2003-12-17

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  BALERAS FRANCOIS ,  DELAGUILLAUMIE FANNY ,  ZUSSY MARC

Inventor： BALERAS FRANCOIS ,  DELAGUILLAUMIE FANNY ,  ZUSSY MARC

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525

CPC classification number: H01L23/525 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: The invention concerns a method for making a wafer level electronic chip scale package, the wafer comprising at least one chip and said at least one chip including input/output contact pads on one surface of the wafer called front side, the method comprising the following steps: a) forming, by means of a mold or a complex stencil, an insulating stress-relaxing layer on said front surface, said relaxation layer covering the wafer front surface with a raised part including access wells at the input/output contact pads, and elsewhere, projecting parts designed to relax the stresses, each projecting part having a stepped shape comprising at least one prominent zone and at least one zone, recessed relative to said prominent zone, designed to support an electrical bond pad; b) forming electrically conductive tracks on the relaxation layer to connect the input/output contact pads to the corresponding electrical bond pads. The invention also concerns a mould or complex stencil for making a chip scale package using said inventive method as well as the resulting package itself.

Abstract translation: 本发明涉及一种用于制造晶片级电子芯片尺寸封装的方法，所述晶片包括至少一个芯片，并且所述至少一个芯片包括在晶片的被称为前侧的一个表面上的输入/输出接触焊盘，所述方法包括以下步骤 ：a）借助于模具或复合模版在所述前表面上形成绝缘应力缓和层，所述弛豫层用包括输入/​​输出接触焊盘处的通路阱的凸起部分覆盖晶片前表面，以及 在其他地方，设计用于放松应力的突出部分，每个突出部分具有阶梯形状，包括至少一个突出区域和至少一个区域，相对于所述突出区域凹入，设计成支撑电键合焊盘; b）在松弛层上形成导电迹线以将输入/输出接触焊盘连接到相应的电接合焊盘。 本发明还涉及用于使用所述发明方法制造芯片级封装的模具或复杂模板以及所得封装本身。

公开(公告)号：FR3000293B1

公开(公告)日：2015-02-20

申请号：FR1262737

申请日：2012-12-21

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： FOURNEL FRANK ,  MORICEAU HUBERT ,  ZUSSY MARC

IPC: H01L21/265 ,  H01L21/30

公开(公告)号：FR2964048B1

公开(公告)日：2012-09-21

申请号：FR1056863

申请日：2010-08-30

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MORICEAU HUBERT ,  ARGOUD MAXIME ,  MORALES CHRISTOPHE ,  ZUSSY MARC

IPC: B05D5/00

公开(公告)号：FR2960340B1

公开(公告)日：2012-06-29

申请号：FR1053987

申请日：2010-05-21

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： FOURNEL FRANK ,  BALLY LAURENT ,  ZUSSY MARC ,  JOURDE DOMINIQUE

IPC: H01L21/00