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    CIRCUIT INTEGRE PHOTONIQUE ET PROCEDE DE FABRICATION
    2.
    发明专利
    CIRCUIT INTEGRE PHOTONIQUE ET PROCEDE DE FABRICATION 未知

    公开(公告)号：FR3007589A1

    公开(公告)日：2014-12-26

    申请号：FR1355991

    申请日：2013-06-24

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  CREMER SEBASTIEN

    IPC: H01S5/026

    Abstract: Circuit intégré photonique, comprenant une couche de silicium contenant un guide d'ondes (GO) et au moins un autre composant photonique, une première région isolante (4) disposée au dessus d'une première face (F1) de la couche de silicium et encapsulant un ou plusieurs niveaux de métallisation (M1-M4), une deuxième région isolante (9) disposée au dessus d'une deuxième face (F2) de la couche de silicium et encapsulant au moins le milieu amplificateur (800) d'une source laser (SL) optiquement couplée avec le guide d'ondes (GO).

    PROCEDE DE FABRICATION D'UN CIRCUIT INTEGRE PHOTONIQUE COUPLE OPTIQUEMENT A UN LASER EN UN MATERIAN III-V
    4.
    发明专利
    PROCEDE DE FABRICATION D'UN CIRCUIT INTEGRE PHOTONIQUE COUPLE OPTIQUEMENT A UN LASER EN UN MATERIAN III-V 未知

    公开(公告)号：FR3024910A1

    公开(公告)日：2016-02-19

    申请号：FR1457861

    申请日：2014-08-18

    Applicant: ST MICROELECTRONICS CROLLES 2

    Inventor： CHANTRE ALAIN ,  CREMER SEBASTIEN

    IPC: G02B6/13 ,  G02B6/42 ,  H01S5/026

    Abstract: L'invention concerne un procédé de fabrication d'un circuit intégré comprenant des composants photoniques (19, 21, 23, 25) sur silicium et un laser (59) en un matériau III-V, le procédé comprenant les étapes successives suivantes : a) prévoir une couche de silicium (3) reposant sur une première couche isolante reposant sur un support ; b) graver des premières tranchées (1, 1') à travers la couche de silicium (3) en s'arrêtant sur la première couche isolante et recouvrir les premières tranchées d'une couche de nitrure de silicium (13) ; c) graver des deuxièmes tranchées (15) à travers une partie seulement de l'épaisseur de la couche de silicium (3) ; d) remplir les premières et deuxièmes tranchées d'oxyde de silicium (17) et aplanir ; e) éliminer le support et la première couche isolante ; et f) coller, du côté de la face arrière (F1), une plaque comportant une hétérostructure III-V.

    METHOD FOR MANUFACTURING SELF-ALIGNED VERTICAL BIPOLAR TRANSISTOR
    5.
    发明专利
    METHOD FOR MANUFACTURING SELF-ALIGNED VERTICAL BIPOLAR TRANSISTOR 失效

    公开(公告)号：JP2001244275A

    公开(公告)日：2001-09-07

    申请号：JP2000283976

    申请日：2000-09-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

    IPC: H01L29/73 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a self-aligned vertical bipolar transistor. SOLUTION: The method for manufacturing the bipolar transistor comprises a process in which a base region 8 having an extrinsic base 800 and an intrinsic base is formed. The method comprises a process which forms an emitter region comprising an emitter block having a comparatively narrow lower part arranged in an emitter window formed above the intrinsic base. When the extrinsic base is formed, the implantation of impurities is executed so as to be self-aligned with respect to the emitter window, by being separated by a predetermined distance from the boundary in the lateral direction of the emitter window on both sides of the emitter window after the emitter window is prescribed and before the emitter block is formed.

    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR
    6.
    发明专利
    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR 失效

    公开(公告)号：JP2001196385A

    公开(公告)日：2001-07-19

    申请号：JP2000353964

    申请日：2000-11-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To propose a vertical bipolar transistor which has a reduced low-frequency noise and allowable static parameters. SOLUTION: This vertical bipolar transistor includes an intrinsic collector 4 on an extrinsic collector layer 2 buried in a semiconductor substrate, a side separation area 5 surrounding the upper part of the intrinsic collector 4, an offset extrinsic collector well 60, a base 8 which is arranged on the intrinsic collector 4 and side separation area 5 and is composed of a semiconductor area including at least one silicon layer, and two doped emitters 11 surrounded with the base 8. The emitters 11 include a first part 110 which is made of single crystal and is directly in contact with the upper surface in the predetermined window 800, and a second part 111 formed of polycrystal. These two parts are isolated by an isolated oxide layer 112 arranged at an optional distance apart from an emitter base joint part.

    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF
    7.
    发明专利
    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF 失效

    公开(公告)号：JP2000031155A

    公开(公告)日：2000-01-28

    申请号：JP15604999

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To reduce low frequency noise while sustaining accurate current amplification factor by obtaining an emitter region of single crystal silicon touching the upper layer of a stack, e.g. silicon of an upper encapsulation layer of the stack, directly on a window. SOLUTION: On a silicon substrate 1, a buried extrinsic collector layer 2 doped with n+ by implanting arsenic and two buried layers 3 similarly doped with p+ are formed and a thick n-type single crystal silicon layer 4 is grown epitaxially. Subsequently, an amorphous silicon layer 17 is deposited on a semiconductor block thus formed and etched above an oxide layer 6 to form a window 170 which is then subjected to desorption. Thereafter, a stack 8 is formed, a silicon dioxide layer 9 and a silicon nitride layer 10 are deposited thereon and then the layers 9, 10 are removed from a desired zone to obtain an emitter, i.e., an emitter window 800.

    METHOD FOR SELECTIVELY DOPING INTRINSIC COLLECTOR OF VERTICAL BIPOLAR TRANSISTOR HAVING EPITAXIAL BASE
    8.
    发明专利
    METHOD FOR SELECTIVELY DOPING INTRINSIC COLLECTOR OF VERTICAL BIPOLAR TRANSISTOR HAVING EPITAXIAL BASE 失效

    公开(公告)号：JPH11354537A

    公开(公告)日：1999-12-24

    申请号：JP15606599

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHARY SCHWARZMANN

    IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To increase the operating speed of a transistor, by executing the injection of a first dopant into the intrinsic collector of the transistor before nonselective epitaxy and the injection of a second dopant into the inner part of the collector at a smaller injected amount and with lower energy than the first dopant through an epitaxially grown stack. SOLUTION: The operating speed of a transistor is the value of the frequency (cut-off frequency of the current amplification factor) of the transistor and the value of the maximum oscillation frequency. The injection of a first dopant into an intrinsic collector 4 in a silicon substrate 1 is executed before the formation of a stack 8 which is formed in an intrinsic base and this injection is high- energy injection. The injection of a second dopant into the collector 4 is executed through an epitaxial base and the injected amount of the second dopant is 1/10 as small as that of the first dopant. Therefore, the defect level in the stack 8 becomes very low and, as a result, a thinner intrinsic base can be obtained and the speed of the transistor increases accordingly.

    9.
    发明专利
    未知

    公开(公告)号：DE69935472D1

    公开(公告)日：2007-04-26

    申请号：DE69935472

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHWARTZMANN THIERRY

    IPC: H01L21/331 ,  H01L29/73 ,  H01L21/265 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: Selective doping of the intrinsic collector of a vertical bipolar transistor comprises high energy dopant implantation before epitaxy and lower energy and lower dose dopant implantation after epitaxy of a silicon germanium heterojunction base. Selective doping of the intrinsic collector of a vertical bipolar transistor is carried out by (a) forming the intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate; (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well; (c) effecting a first dopant implantation in the intrinsic collector through a first implantation window above the intrinsic collector; (d) forming a silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a silicon and silicon germanium multilayer (8); and (e) effecting a second lower energy and lower dose dopant implantation in the intrinsic collector across the multilayer in a second implantation window located within the first implantation window above the multilayer (8) and self-aligned with the emitter.

    10.
    发明专利
    未知

    公开(公告)号：FR2868203B1

    公开(公告)日：2006-06-09

    申请号：FR0450610

    申请日：2004-03-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  CHEVALIER PASCAL

    IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/10 ,  H01L29/737

    Abstract: A method forms a bipolar transistor in a semiconductor substrate of a first conductivity type. The method includes: forming on the substrate a single-crystal silicon-germanium layer; forming a heavily-doped single-crystal silicon layer of a second conductivity type; forming a silicon oxide layer; opening a window in the silicon oxide and silicon layers; forming on the walls of the window a silicon nitride spacer; removing the silicon-germanium layer from the bottom of the window; forming in the cavity resulting from the previous removal a heavily-doped single-crystal semiconductor layer of the second conductivity type; and forming in said window the emitter of the transistor.

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