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    INTEGRATED OPTOELECTRONIC DEVICE WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF
    3.
    发明申请
    INTEGRATED OPTOELECTRONIC DEVICE WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF 审中-公开
    具有波导的集成光电装置及其制造工艺

    公开(公告)号：WO2014006570A1

    公开(公告)日：2014-01-09

    申请号：PCT/IB2013055430

    申请日：2013-07-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAGANI ALBERTO ,  MOTTA ALESSANDRO ,  LOI SARA

    IPC: G02B6/12 ,  G02B6/43

    CPC classification number: H01L31/02327 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/43 ,  H01L31/103 ,  H01L31/125

    Abstract: An integrated electronic device, delimited by a first surface (Si) and by a second surface (S2) and including: a body (2) made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector (30) and an emitter (130); and an optical path (OP), which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

    Abstract translation: 一种由第一表面（Si）和第二表面（S2）界定并包括：由半导体材料制成的主体（2）的集成电子器件，其中形成有至少一个光电元件，所述至少一个光电元件选自检测器（30） 和发射器（130）; 以及光路（OP），其至少部分地是引导型的并且在所述第一表面和所述第二表面之间延伸，所述光路穿过所述主体。 光电子部件通过光路光耦合到自由空间的第一部分和自由空间的第二部分，其分别布置在第一和第二表面的上方和下方。

    INTEGRATED ELECTRONIC DEVICE FOR MONITORING PRESSURE WITHIN A SOLID STRUCTURE
    5.
    发明申请
    INTEGRATED ELECTRONIC DEVICE FOR MONITORING PRESSURE WITHIN A SOLID STRUCTURE 审中-公开
    一种用于在固体结构内监测压力的集成电子装置

    公开(公告)号：WO2014155326A3

    公开(公告)日：2014-12-18

    申请号：PCT/IB2014060203

    申请日：2014-03-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAGANI ALBERTO

    IPC: G01L25/00 ,  G01L1/14

    CPC classification number: G01L1/142 ,  G01L1/144 ,  G01L1/148 ,  G01L1/26 ,  G01L25/00

    Abstract: The invention relates to an integrated electronic device (400; 400a; 500, 500'; 600, 600'; 700, 700') on a semiconductor material chip for detecting the pressure related to a force (F) applied in a predetermined direction (d) within a solid structure. The device comprises: - an integrated element (51) defined by an operating surface of the chip (52) that is substantially orthogonal to the direction (d) of application of the force; first (53) and second (54) conductive elements accommodated within the substrate element (51) and configured to face the operating surface; a measure module (55) accommodated within the substrate element and comprising first (56) and second (57) measurement terminals which are electrically connected to the first (53) and second (54) conductive elements, respectively; a detecting element (58) arranged in the predetermined direction (d) such that the operating surface (52) is sandwiched between the first (53) and second (54) conductive elements and this detecting element ( 58 ); - an insulating layer (59) suitable to coat at least the operating surface in order to galvanically insulate the first (53) and second (54) conductive elements. The device comprises a layer of dielectric material (510, 510') which is at least sandwiched between the detecting element (58) and the insulating layer (59). The layer of dielectric material is elastically deformable following the application of the force (F) in the predetermined direction to change an electromagnetic coupling between the detecting element (58) and the above-mentioned first (53) and second (54) conductive elements.

    Abstract translation: 本发明涉及在半导体材料芯片上的集成电子器件（400; 400a; 500,500'; 600,600'; 700,700'），用于检测与在预定方向上施加的力（F） d）坚实的结构。 该装置包括： - 由芯片（52）的操作表面限定的集成元件（51），该集成元件基本上与施加力的方向（d）正交; 第一导电元件（53）和第二导电元件（54），所述导电元件容纳在所述衬底元件（51）内并且构造成面对所述操作表面; 测量模块（55），所述测量模块（55）容纳在所述衬底元件内并且包括分别电连接到所述第一导电元件（53）和所述第二导电元件（54）的第一测量端子（56）和第二测量端子（57）; 检测元件（58），其沿预定方向（d）布置，使得操作表面（52）夹在第一导电元件（53）和第二导电元件（54）与该检测元件（58）之间; - 绝缘层（59），其适于涂覆至少所述操作表面以电绝缘所述第一导电元件（53）和所述第二导电元件（54）。 该装置包括至少夹在检测元件（58）和绝缘层（59）之间的一层介电材料（510,510'）。 在沿预定方向施加力（F）之后，介电材料层可弹性变形，以改变检测元件（58）与上述第一导电元件（53）和第二导电元件（54）之间的电磁耦合。

    PACKAGED ELECTRONIC DEVICE COMPRISING INTEGRATED ELECTRONIC CIRCUITS HAVING TRANSCEIVING ANTENNAS
    7.
    发明申请
    PACKAGED ELECTRONIC DEVICE COMPRISING INTEGRATED ELECTRONIC CIRCUITS HAVING TRANSCEIVING ANTENNAS 审中-公开
    包含收发天线的集成电子电路的包装电子设备

    公开(公告)号：WO2013128348A3

    公开(公告)日：2014-01-23

    申请号：PCT/IB2013051422

    申请日：2013-02-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PAGANI ALBERTO

    IPC: H01L23/48

    CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A base (2) carries a first chip (3) and a second chip (4) oriented differently with respect to the base and packaged in a package (6). Each chip integrates an antenna and a magnetic via (13). A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips (3, 4) even if the magnetic path is interrupted, and is formed by a first stretch (5c) coupled between the first magnetic-coupling element (13) of the first chip and the first magnetic-coupling element (12) of the second chip, and a second stretch (5f) coupled between the second magnetic-coupling element (12) of the first chip and the second magnetic-coupling element (13) of the second chip. The first stretch has a parallel portion (5c1, 5c3) extending parallel to the faces (2a, 2b) of the base. The first and second stretches have respective transverse portions (5i1, 5i2) extending on the main surfaces of the second chip, transverse to the parallel portion.

    Abstract translation: 基座（2）承载相对于基座不同定向并封装在封装（6）中的第一芯片（3）和第二芯片（4）。 每个芯片集成天线和磁通（13）。 磁耦合路径连接芯片，形成磁路，即使磁路被中断也能够在芯片（3,4）之间传递信号和电力，并且通过耦合在第一磁性体之间的第一拉伸（5c）形成 第一芯片的耦合元件（13）和第二芯片的第一磁耦合元件（12）以及耦合在第一芯片的第二磁耦合元件（12）和第二芯片之间的第二拉伸（5f） 第二芯片的磁耦合元件（13）。 第一拉伸具有平行于基部的表面（2a，2b）延伸的平行部分（5c1,5c3）。 第一和第二延伸部具有横向于平行部分的在第二芯片的主表面上延伸的相应横向部分（5i1,5i2）。

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