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公开(公告)号：FR3122024A1
公开(公告)日：2022-10-21
申请号：FR2104087
申请日：2021-04-20
Applicant: ST MICROELECTRONICS GRENOBLE 2 , ST MICROELECTRONICS SRL
Inventor： VALENCIA RISSETTO LEONARDO , TOMAIUOLO FRANCESCO , DE COSTANTINI DIEGO
Abstract: Dans le procédé de gestion de données (300) pour une mémoire non volatile programmable bit à bit, le stockage de nouvelles données (NewDat) en un emplacement mémoire (Loc) d’un mot-mémoire comprend : - une étape de mesure (302) qui mesure les données précédentes (FormDat) stockées dans l’emplacement mémoire ; - le calcul (303) d’une première et d’une deuxième quantification (Q1, Q2) des opérations de programmation bit à bit correspondant aux bits des nouvelles données (NewDat), et d’une inversion complémentaire des nouvelles données (Compl.NewDat), qui sont respectivement différents des bits des données précédentes (FormDat), - une étape de programmation (306) comprenant, si la première quantification (Q1) est strictement supérieure à la deuxième quantification (Q2), la programmation bit à bit des bits de l’inversion complémentaire (305) des nouvelles données (Compl.NewDat) respectivement différents des bits des données précédentes (FormDat), et la programmation d’un drapeau d’inversion (InvFlg) à une valeur marquée. Figure pour l’abrégé : Fig 1
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公开(公告)号：JP2001243778A
公开(公告)日：2001-09-07
申请号：JP2001022134
申请日：2001-01-30
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPANALE FABRIZIO , TOMAIUOLO FRANCESCO , NICOSIA SALVATORE , DE AMBROGGI LUCA GIUSEPPE , KUMAR PROMOD , PASCUCCI LUIGI
Abstract: PROBLEM TO BE SOLVED: To provide a multi-purpose memory device suitable for an application example of a wider range independently of whether reading of data is required or not in the asynchronous mode (as in standard memory) in random access or in a synchronous progressive mode in burst type access. SOLUTION: A memory device recognizes modes of access and reading required by a microprocessor, also enables performing self-conditioning of its internal circuit based on such a recognition to perform reading data in a required mode. At the time, an additional external control signal is not required, and sacrifice is not forced in an access time and a reading time as compared with obtained one in the case of a memory device constituted specifically for any one of operation modes for constitution of the same manufacturing technology and conventional technology.
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公开(公告)号：DE60306488D1
公开(公告)日：2006-08-10
申请号：DE60306488
申请日：2003-02-27
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号：DE60011035T2
公开(公告)日：2004-09-16
申请号：DE60011035
申请日：2000-03-02
Applicant: ST MICROELECTRONICS SRL
Inventor： DE AMBROGGI LUCA GIUSEPPE , CAMPANELE FABRIZIO , KUMAR PROMOD , NICOSIA SALVATORE , TOMAIUOLO FRANCESCO
Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).
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公开(公告)号：DE60011035D1
公开(公告)日：2004-07-01
申请号：DE60011035
申请日：2000-03-02
Applicant: ST MICROELECTRONICS SRL
Inventor： DE AMBROGGI LUCA GIUSEPPE , CAMPANELE FABRIZIO , KUMAR PROMOD , NICOSIA SALVATORE , TOMAIUOLO FRANCESCO
Abstract: A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_O), organized in rows and columns; the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), contemplates dividing said number of packets (REDUNDANCY) in two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).
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Patent Agency Ranking
公开(公告)号：ITVA20000015A1
公开(公告)日：2001-11-30
申请号：ITVA20000015
申请日：2000-05-30
Applicant: ST MICROELECTRONICS SRL
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公开(公告)号：IT202100030134A1
公开(公告)日：2023-05-29
申请号：IT202100030134
申请日：2021-11-29
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE AGATINO MASSIMO , CONTE ANTONINO , TOMAIUOLO FRANCESCO , PISASALE MICHELANGELO , RUTA MARCO
IPC: H03M20060101
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公开(公告)号：DE60041263D1
公开(公告)日：2009-02-12
申请号：DE60041263
申请日：2000-10-18
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMAIUOLO FRANCESCO , NICOSIA SALVATORE , PASCUCCI LUIGI
Abstract: A new multipurpose interlaced memory device functions in two different modes: synchronous and asynchronous, using a circuit for detecting address transitions that by acting as a synchronous clock of the system lets the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of cells. The memory device has a buffer for outputting a datum provided with means that for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.
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公开(公告)号：IT202000006109A1
公开(公告)日：2021-09-23
申请号：IT202000006109
申请日：2020-03-23
Applicant: ST MICROELECTRONICS SRL , ST MICROELECTRONICS ROUSSET
Inventor： CONTE ANTONINO , TOMAIUOLO FRANCESCO , LA ROSA FRANCESCO
IPC: H03K20060101
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公开(公告)号：DE60044895D1
公开(公告)日：2010-10-14
申请号：DE60044895
申请日：2000-04-17
Applicant: ST MICROELECTRONICS SRL
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