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公开(公告)号:FR3109239A1
公开(公告)日:2021-10-15
申请号:FR2003730
申请日:2020-04-14
Applicant: ST MICROELECTRONICS ROUSSET , ST MICROELECTRONICS SRL
Inventor: LA ROSA FRANCESCO , CASTALDO ENRICO , GRANDE FRANCESCA , PAGANO SANTI NUNZIO ANTONINO , NASTASI GIUSEPPE , ITALIANO FRANCO
Abstract: Le circuit intégré de mémoire non-volatile (NVM) comprend des cellules mémoires logées dans un caisson semiconducteur (PW1) et comportant chacune un transistor d’état (TEsel, TEnsl) ayant une grille flottante (FG) et une grille de commande (CG), ainsi que des moyens d’effacement configurés, lors d’un cycle d’effacement, pour polariser le caisson semiconducteur (PW1) à une première tension d’effacement (VYP), et, par l’intermédiaire de commutateurs de grille de commande (CGSW), pour polariser des grilles de commande de cellules mémoires sélectionnées (TEsel) à une deuxième tension d’effacement (VNN). Les moyens d’effacement sont configurés pour augmenter le niveau de la première tension d’effacement (VYP) résultant d’une augmentation d’une valeur d’usure (AG) représentative du vieillissement des cellules mémoires, de sorte que le niveau de la première tension d’effacement (VYP) peut être supérieur à un niveau de claquage (HVmax) des commutateurs de grille de commande (CGSW). Figure de l’abrégé : figure 1
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2.
公开(公告)号:ITUA20164741A1
公开(公告)日:2017-12-29
申请号:ITUA20164741
申请日:2016-06-29
Applicant: ST MICROELECTRONICS SRL , ST MICROELECTRONICS CROLLES 2 SAS , ST MICROELECTRONICS ROUSSET
Inventor: CONTE ANTONINO , CASTALDO ENRICO , BIANCHI RAUL ANDRES , LA ROSA FRANCESCO
IPC: G04F10/10
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公开(公告)号:FR3109239B1
公开(公告)日:2022-04-22
申请号:FR2003730
申请日:2020-04-14
Applicant: ST MICROELECTRONICS ROUSSET , ST MICROELECTRONICS SRL
Inventor: LA ROSA FRANCESCO , CASTALDO ENRICO , GRANDE FRANCESCA , PAGANO SANTI NUNZIO ANTONINO , NASTASI GIUSEPPE , ITALIANO FRANCO
Abstract: Le circuit intégré de mémoire non-volatile (NVM) comprend des cellules mémoires logées dans un caisson semiconducteur (PW1) et comportant chacune un transistor d’état (TEsel, TEnsl) ayant une grille flottante (FG) et une grille de commande (CG), ainsi que des moyens d’effacement configurés, lors d’un cycle d’effacement, pour polariser le caisson semiconducteur (PW1) à une première tension d’effacement (VYP), et, par l’intermédiaire de commutateurs de grille de commande (CGSW), pour polariser des grilles de commande de cellules mémoires sélectionnées (TEsel) à une deuxième tension d’effacement (VNN). Les moyens d’effacement sont configurés pour augmenter le niveau de la première tension d’effacement (VYP) résultant d’une augmentation d’une valeur d’usure (AG) représentative du vieillissement des cellules mémoires, de sorte que le niveau de la première tension d’effacement (VYP) peut être supérieur à un niveau de claquage (HVmax) des commutateurs de grille de commande (CGSW). Figure de l’abrégé : figure 1
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4.
公开(公告)号:ITUA20164739A1
公开(公告)日:2017-12-29
申请号:ITUA20164739
申请日:2016-06-29
Applicant: ST MICROELECTRONICS SRL , ST MICROELECTRONICS CROLLES 2 SAS , ST MICROELECTRONICS ROUSSET
Inventor: CONTE ANTONINO , CASTALDO ENRICO , BIANCHI RAUL ANDRES , LA ROSA FRANCESCO
IPC: G04F10/10
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公开(公告)号:DE602006009091D1
公开(公告)日:2009-10-22
申请号:DE602006009091
申请日:2006-07-06
Applicant: ST MICROELECTRONICS SRL
Inventor: CASTALDO ENRICO , CONTE ANTONINO , LO GIUDICE GIANBATTISTA
Abstract: There is disclosed an integrated control circuit (3) for a charge pump (1). The integrated circuit comprises a first device (112,N1,N2,R,12) suitable for regulating the output voltage (Vout) of the charge pump (1) and a second device (113,M10,M11,C11,11) suitable for increasing the output voltage (Vout) from the charge pump with a set ramp. The integrated circuit comprises means (111) suitable for activating said first device and providing it with a first value of a supply signal (Ireg) in a first period of time (A) and suitable for activating said second device and for providing it with a second value (Iramp) of the supply signal that is greater than the first value in a second period of time (C) after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value (Vlow) to a second value (Vhigh) that is greater than the first value, said second value being fixed by the reactivation of the first device.
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公开(公告)号:ITVA20020020A1
公开(公告)日:2003-09-04
申请号:ITVA20020020
申请日:2002-03-04
Applicant: ST MICROELECTRONICS SRL
Inventor: CASTALDO ENRICO , CONTE ANTONINO
IPC: H02M3/07
Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.
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7.
公开(公告)号:ITMI20120650A1
公开(公告)日:2013-10-20
申请号:ITMI20120650
申请日:2012-04-19
Applicant: ST MICROELECTRONICS SRL
Inventor: CASTALDO ENRICO , CONTE ANTONINO , PAGANO SANTI NUNZIO ANTONINO , RINALDI STEFANIA
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公开(公告)号:DE602004010226D1
公开(公告)日:2008-01-03
申请号:DE602004010226
申请日:2004-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor: CASTALDO ENRICO , CONTE ANTONINO , TORRISI SALVATORE , SAMBATARO VINCENZO
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公开(公告)号:DE60304311T2
公开(公告)日:2006-12-21
申请号:DE60304311
申请日:2003-06-24
Applicant: ST MICROELECTRONICS SRL
Inventor: CONTE ANTONINO , CASTALDO ENRICO
IPC: H02M3/07
Abstract: The circuit has a voltage comparator (400) to compare a charge pump output voltage and a reference voltage. A clock control (425) conditions a charge pump clocking based on the comparison result. The comparator has a sampling unit for sampling the charge pump output voltage at a sampling rate. A frequency divider (415) and frequency selection state machine (410) controls the sampling rate based on voltage comparison result. Independent claims are also included for the following: (a) an integrated circuit including a charge pump voltage generator and a charge pump regulator circuit (b) a method of regulating an output voltage of a charge-pump voltage generator.
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公开(公告)号:DE60304311D1
公开(公告)日:2006-05-18
申请号:DE60304311
申请日:2003-06-24
Applicant: ST MICROELECTRONICS SRL
Inventor: CONTE ANTONINO , CASTALDO ENRICO
IPC: H02M3/07
Abstract: The circuit has a voltage comparator (400) to compare a charge pump output voltage and a reference voltage. A clock control (425) conditions a charge pump clocking based on the comparison result. The comparator has a sampling unit for sampling the charge pump output voltage at a sampling rate. A frequency divider (415) and frequency selection state machine (410) controls the sampling rate based on voltage comparison result. Independent claims are also included for the following: (a) an integrated circuit including a charge pump voltage generator and a charge pump regulator circuit (b) a method of regulating an output voltage of a charge-pump voltage generator.
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