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公开(公告)号：FR2792760B1
公开(公告)日：2001-08-17
申请号：FR9905328
申请日：1999-04-23
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE
IPC: G11C7/12 , G11C11/419 , G11C7/00
Abstract: An integrated circuit includes an array of memory cells that are selected by rows and read by columns. The columns are first precharged by an internal signal to then read the memory cells. The read is responsive to an edge of a clock signal and the read is of an unknown delay. A multiplexer output provides the internal signal. The multiplexer includes a plurality of inputs electrically connected to delay lines of different delay sizes that receive the edge of the clock signal. A multiplexer control circuit selects a delay line to provide the internal signal as soon as possible after the unknown delay.
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公开(公告)号：FR2792760A1
公开(公告)日：2000-10-27
申请号：FR9905328
申请日：1999-04-23
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE
IPC: G11C7/12 , G11C11/419 , G11C7/00
Abstract: The integrated circuit produces an event in reaction to a front of clock signal (CK) with an unknown delay (delta), and comprises the means for obtaining an internal precharge signal (P) which include a set of delay lines (D1,D2,D3,D4) of different lengths receiving the clock signal, nd a multiplexer (12) receiving the delayed signals and delivering the internal signal (P) to the memory circuit (1). The multiplexer (12) is controlled by an auto-test circuit (13). The memory circuit comprises at least one reference element which generates a reference front in reaction to the clock signal front with a delay greater than the unknown delay. In the second embodiment, the circuit configuration allows a change of the selection of the delay line in the course of functioning, and comprises a control circuit connected to the multiplexer for the delivery of internal signal as early as possible after the lapse of unknown delay, and a set of comparators receiving the delayed signals and the reference fronts at two inputs and delivering output signals to the control circuit. The integrated circuit comprises an array of memory cells with row selection by an address signal (A), with access for column reading by the bit lines, wherein the input clock signal (CK) isused for synchronization of the address signal, the event is the column reading, and the internal signal (P) is that for precharging the bit lines. The reference element is a supplementary column positioned so that the reading is slower than that of other columns. The circuit adjustment in the test mode includes the following steps: (a) the selection of the shortest delay line; (b) the input of a predetermined signal; (c) the termination of test if the internal signal occurs before the event in reaction to the front signal; and (d) the selection of the next length delay line and return to the steps (b) and (c) if the condition is not met.
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公开(公告)号：FR2857149A1
公开(公告)日：2005-01-07
申请号：FR0307983
申请日：2003-07-01
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE , GENEVAUX FRANCK
Abstract: The circuit has a memory device with a dummy path having a reference column with two reference bit lines (blfdum, bltdum). One of two reference memory cells is activated by a dummy word line and is programmed to discharge the line (bltdum). The line (blfdum) that is discharged by drain currents of access transistors in their off state controls activation of a read amplifier. The other memory cell is programmed with data opposed to that in the former cell. An independent claim is also included for a procedure for controlling reader amplifiers.
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公开(公告)号：FR2857091A1
公开(公告)日：2005-01-07
申请号：FR0307984
申请日：2003-07-01
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE
Abstract: The circuit has a temperature detection device (DTM) to detect the temperature of an integrated circuit. The device has field effect transistors (T1-T3) that are connected in parallel and in their blocked state. A resistive unit (T4) is connected in series with the transistors. An inverter (IV) senses the value of voltage present at the common terminal between the blocked transistors and the resistive unit. An independent claim is also included for a method for detecting the temperature of an integrated circuit.
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公开(公告)号：FR2871921A1
公开(公告)日：2005-12-23
申请号：FR0406532
申请日：2004-06-16
Applicant: ST MICROELECTRONICS SA
Inventor： DRAY CYRILLE , BARASINSKI SEBASTIEN , LASSEUGUETTE JEAN , FREY CHRISTOPHE , FOURNEL RICHARD
Abstract: L'invention concerne un dispositif de mémoire, comprenant au moins une ligne d'écriture segmentée (10) formée d'au moins un segment d'écriture, dotée de moyens de programmation (90), lesdits moyens de programmation (90) étant commandés par des moyens d'adressage de ligne (190) en mode écriture dudit dispositif de mémoire, pour programmer au moins une cellule mémoire (30) couplée à ladite ligne d'écriture segmentée, une ligne de bit de lecture (150) étant reliée à un circuit de lecture (110) pour lire le contenu de ladite cellule en mode lecture dudit dispositif de mémoire, caractérisé en ce que ladite ligne de bit de lecture coopère en mode écriture avec lesdits moyens d'adressage de ligne pour commander lesdits moyens de programmation de ladite ligne d'écriture segmentée.
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Patent Agency Ranking
公开(公告)号：FR2871922A1
公开(公告)日：2005-12-23
申请号：FR0406600
申请日：2004-06-17
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE , TURGIS DAVID , LAFONT JEAN CHRISTOPHE
IPC: G11C11/412 , G11C11/40 , H03K3/356
Abstract: L'invention concerne une cellule mémoire (1), qui comprend :-un bistable (2) présentant des bornes de lecture/écriture complémentaires;-une ligne d'écriture de bit à 1 (wb11);-un premier transistor interrupteur (T4) entre la ligne d'écriture de bit à 1 et la borne, sa grille étant connectée à une ligne de sélection de mot (Wll);-une ligne d'écriture de bit à 0 (wb10);-un second transistor interrupteur (T3) entre la ligne d'écriture de bit à 0 et la borne, sa grille étant connectée à une ligne de sélection de mot (W12);-une ligne de lecture de bit (b1r);-des transistors de lecture (T1, T2), dont une grille est connectée à une borne de lecture/écriture et dont l'autre est connectée à une ligne de sélection de mot.L'invention permet notamment de réduire la surface et la complexité d'une cellule mémoire.
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公开(公告)号：FR2857149B1
公开(公告)日：2005-12-16
申请号：FR0307983
申请日：2003-07-01
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE , GENEVAUX FRANCK
Abstract: The circuit has a memory device with a dummy path having a reference column with two reference bit lines (blfdum, bltdum). One of two reference memory cells is activated by a dummy word line and is programmed to discharge the line (bltdum). The line (blfdum) that is discharged by drain currents of access transistors in their off state controls activation of a read amplifier. The other memory cell is programmed with data opposed to that in the former cell. An independent claim is also included for a procedure for controlling reader amplifiers.
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公开(公告)号：FR2826495B1
公开(公告)日：2005-03-11
申请号：FR0108270
申请日：2001-06-22
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE
Abstract: A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between the first node linked to the bit line and a third node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.
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公开(公告)号：FR2793064A1
公开(公告)日：2000-11-03
申请号：FR9905726
申请日：1999-04-30
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE
IPC: G11C11/412 , G11C11/413 , G11C11/40
Abstract: The static memory unit comprises an array of rows and columns of memory cells, where each column is connected between high (VDD) and low (GND) supply voltage terminals and comprises at least one MOS (Metal Oxide Superconductor) transistors (12,14) connected in series with the column, and means for application to control signal for transistor blocking and a passage of the column to stand-by mode. The memory unit comprises a first MOS transistor (12) of p-type conductivity channel on the side of high supply voltage terminal (VDD), e.g. 1 V, and a second MOS transistor (14) of n-type conductivity channel on the side of low supply voltage terminal (GND), which is e.g. grounded. In the second embodiment, the column ensemble also comprises diodes e.g. transistors connected as diodes, connected in parallel with the first and second transistors, to ensure functioning in the case of failure of transistors. Each memory cell contains two inverters in anti-parallel connection, wherein the input of the first inverter and the output of the second inverter are connected to the first bit line via a first interrupter, e.g. a transistor, the input of the second inverter and the output of the first inverter are connected to the second bit line via a second interrupter. Each inverter comprises two MOS transistors, one with p-type and the other with n-type conductivity channel. At least one of the transistors (12,14) connected in series is chosen so that its length of gate, e.g. 0.3 micrometer, is greater than that of the transistors of memory cells .g. 0.25 micrometer.
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公开(公告)号：FR2793064B1
公开(公告)日：2004-01-02
申请号：FR9905726
申请日：1999-04-30
Applicant: ST MICROELECTRONICS SA
Inventor： FREY CHRISTOPHE
IPC: G11C11/412 , G11C11/413 , G11C11/40
Abstract: A SRAM including an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage, which includes at least one MOS transistor in series with each column, and circuitry for applying to the at least one MOS transistor a turn-off control signal to enter a stand-by mode, whereby the overall resistance of the column and of the at least one transistor increases in stand-by mode.
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