公开(公告)号：JP2000049295A

公开(公告)日：2000-02-18

申请号：JP19889599

申请日：1999-07-13

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE ,  GUELEN JOS ,  LUNARDI GENEVIEVE ,  BANVILLET HENRI ,  OBERLIN JEAN-CLAUDE ,  MADDALON CATHERINE

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method which has compatibility with the existing CMOS components manufacturing process in manufacturing a capacitor, having little possibility of causing the dielectric breakdown. SOLUTION: A first metal layer is deposited and etched with leaving a region 12, corresponding to a capacitor plate and contact region 13 on the first metal layer, an input layer 15 is deposited between metallization layers, a first opening is formed into an upper part of the capacitor plate 12, a thin insulation layer 17 is deposited, a second opening 20 is formed into an upper part of the contact region, a second metal layer 24 is deposited for completely filling the opening 20, a physical-chemical etching is applied to suppress the outside region of the second metal layer, and a third metal layer is deposited to cause to be left at positions 31, 32 on the third metal layer above the contact region and capacitor region.

公开(公告)号：FR2781603B1

公开(公告)日：2000-10-06

申请号：FR9809437

申请日：1998-07-21

Applicant: ST MICROELECTRONICS SA

Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE ,  GUELEN JOS ,  LUNARDI GENEVIEVE ,  BANVILLET HENRI ,  OBERLIN JEAN CLAUDE ,  MADDALON CATHERINE

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L21/3205 ,  H01L21/8234

Abstract: Process involves depositing and etching metal layer for region (12) corresponding to a capacitance plate and area (13) contacting a higher layer; depositing insulating layer; forming hole above the plate, depositing thin insulating layer; forming 2nd hole above contact zone; depositing 2nd metal layer; etching 2nd metal layer except in hole-filling regions; and depositing 3rd metal layer (31, 32). The 1st and 2nd metal layers are tungsten, and the 3rd metal layer is Al-Cu. The 1st hole has inclined walls, while the 2nd hole has straight walls.

公开(公告)号：FR2781603A1

公开(公告)日：2000-01-28

申请号：FR9809437

申请日：1998-07-21

Applicant: ST MICROELECTRONICS SA

Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE ,  GUELEN JOS ,  LUNARDI GENEVIEVE ,  BANVILLET HENRI ,  OBERLIN JEAN CLAUDE ,  MADDALON CATHERINE

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L21/3205 ,  H01L21/8234

Abstract: Process involves depositing and etching metal layer for region (12) corresponding to a capacitance plate and area (13) contacting a higher layer; depositing insulating layer; forming hole above the plate, depositing thin insulating layer; forming 2nd hole above contact zone; depositing 2nd metal layer; etching 2nd metal layer except in hole-filling regions; and depositing 3rd metal layer (31, 32). The 1st and 2nd metal layers are tungsten, and the 3rd metal layer is Al-Cu. The 1st hole has inclined walls, while the 2nd hole has straight walls.