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    MANUFACTURE FOR BIPOLAR TRANSISTOR
    1.
    发明专利
    MANUFACTURE FOR BIPOLAR TRANSISTOR 失效

    公开(公告)号：JP2000286270A

    公开(公告)日：2000-10-13

    申请号：JP2000068526

    申请日：2000-03-13

    Applicant: ST MICROELECTRONICS SA

    Inventor： GRIS YVON ,  TROILLARD GERMAINE

    IPC: H01L29/417 ,  H01L21/225 ,  H01L21/265 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732

    Abstract: PROBLEM TO BE SOLVED: To reduce resistance of a base-emitter junction by a method, wherein a silicon nitride, and next a silicon oxide are deposited and etched, and these layers are anisotropically etched and cleaned, and a silicon oxide layer is re- etched. SOLUTION: A thermal oxide 16 is grown on the surface of a substrate 11 as the bottom part of a window W, and on the side face exposed of a polysilicon layer 13. Next, a base region 17 is formed by injection through the thin oxide 16. Next, a silicon nitride layer 18 is equiangularly deposited, next a spacer is formed, and therefore a silicon oxide layer 19 of, for example a thickness of about 150 nm is equiangularly deposited. Next, the oxide layer 19 is anisotropically etched, and the spacer is left behind, and thereafter the nitride layer 18 and the thermal oxide layer 16 are anisotropically etched. Next, cleaning is preferably performed at three stages, and the spacer formed by the layer 19 on a wall of the window W is partially re-etched. As a result, a flare-type profile can be obtained.

    Method for depositing single crystal silicon region
    3.
    发明专利
    Method for depositing single crystal silicon region 审中-公开
    沉积单晶硅区域的方法

    公开(公告)号：JPH11274171A

    公开(公告)日：1999-10-08

    申请号：JP1441499

    申请日：1999-01-22

    Applicant: St Microelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

    Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE

    IPC: H01L29/73 ,  C30B25/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L29/732

    CPC classification number: C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66287 ,  Y10S117/913

    Abstract: PROBLEM TO BE SOLVED: To deposit silicon at a low temperature, by deciding a window on a single crystal silicon substrate, and generating an inter-lattice defect in terms of atoms at a specified rate in the window.
    SOLUTION: A window 13 is given on a single crystal silicon substrate 11. The surface of the area of a layer which is not covered by the window is processed in a way that a lattice defect is generated at the rate of one percent in terms of atoms to the depth of below 5 μm in a crystal lattice in a region 14 which is not covered. When the stage of any annealing is not executed immediately after the processing, an upper layer 15 is processed with conditions that a state is that of pressure reduction at the temperature below that at which epitaxial deposition is generally executed, a range is 600-700°C and below 900°C, reaction gas is silane (SiH
    4 ) and pressure reduction is about 0.1×10
    5 Pa (80 Torr). The layer 15 is similar to the substrate 11 but it has single crystal structure following a crystal axis different form the crystal axis of the substrate 11.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：通过在单晶硅衬底上确定窗口并在窗口中以规定的速率产生晶格间缺陷，以便在低温下沉积硅。 解决方案：在单晶硅衬底11上提供窗口13.未被窗口覆盖的层的区域的表面以如下方式进行处理，即以1％的速率产生晶格缺陷， 原子在未被覆盖的区域14中的晶格中的5μm以下的深度。 当在处理之后立即执行任何退火阶段时，上层15的处理条件是在低于通常执行外延沉积的温度下的压力降低的状态，范围为600-700度 ℃，900℃以下，反应气体为硅烷（SiH4），减压约为0.1×10 5 Pa（80托）。 层15与基板11相似，但是具有与基板11的晶轴不同的晶轴的单晶结构。

    4.
    发明专利
    未知

    公开(公告)号：FR2790867B1

    公开(公告)日：2001-11-16

    申请号：FR9903260

    申请日：1999-03-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： GRIS YVON ,  TROILLARD GERMAINE

    IPC: H01L29/417 ,  H01L21/225 ,  H01L21/265 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L21/8222

    Abstract: Bipolar transistor production, comprising etching a silicon oxide layer (19) to form a bell-mouthed opening in which polysilicon is deposited, is new. Production of a bipolar transistor in a first conductivity type semiconductor substrate (11) comprises depositing and doping a polysilicon base contact layer (13), depositing a silicon oxide layer (14) and forming an opening in the two layers, followed by the novel steps of (a) annealing to form an oxide thin film (16) and to harden the silicon oxide layer (14); (b) implanting a second conductivity type dopant; (c) depositing a silicon nitride layer (18); (d) depositing and etching a further silicon oxide layer (19); (e) anisotropically etching the silicon oxide layer (19), the silicon nitride layer (18) and the oxide thin film (16); (f) cleaning while re-etching the silicon oxide layer (19) to form a bell-mouthed opening (W1); (g) depositing a polysilicon layer; and (h) implanting a first conductivity type dopant.

    5.
    发明专利
    未知

    公开(公告)号：DE69719711D1

    公开(公告)日：2003-04-17

    申请号：DE69719711

    申请日：1997-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： GRIS YVON ,  MOURIER JOCELYNE ,  TROILLARD GERMAINE

    IPC: H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

    Abstract: A bipolar transistor (BT) is formed by depositing a polysilicon base layer (23) and then a protective oxide layer (24), forming an emitter-base opening, depositing and etching a polysilicon emitter layer (46) and etching the protective oxide layer (24) and the polysilicon base layer (23) outside the BT zones. Deep trenches are formed by: (a) opening the protective oxide layer and polysilicon base layer combination above a thick oxide zone (5) during formation of the emitter-base opening; (b) etching the thick oxide layer (5) during etching of the protective oxide layer (24); and (c) etching the silicon (2) below the thick oxide during etching of the polysilicon base layer (23). Preferably, the trench is etched to 1-1.5 mu m depth and 0.25-0.5 mu m width.

    8.
    发明专利
    未知

    公开(公告)号：FR2790867A1

    公开(公告)日：2000-09-15

    申请号：FR9903260

    申请日：1999-03-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： GRIS YVON ,  TROILLARD GERMAINE

    IPC: H01L29/417 ,  H01L21/225 ,  H01L21/265 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L21/8222

    Abstract: Bipolar transistor production, comprising etching a silicon oxide layer (19) to form a bell-mouthed opening in which polysilicon is deposited, is new. Production of a bipolar transistor in a first conductivity type semiconductor substrate (11) comprises depositing and doping a polysilicon base contact layer (13), depositing a silicon oxide layer (14) and forming an opening in the two layers, followed by the novel steps of (a) annealing to form an oxide thin film (16) and to harden the silicon oxide layer (14); (b) implanting a second conductivity type dopant; (c) depositing a silicon nitride layer (18); (d) depositing and etching a further silicon oxide layer (19); (e) anisotropically etching the silicon oxide layer (19), the silicon nitride layer (18) and the oxide thin film (16); (f) cleaning while re-etching the silicon oxide layer (19) to form a bell-mouthed opening (W1); (g) depositing a polysilicon layer; and (h) implanting a first conductivity type dopant.

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