公开(公告)号：JP2000049295A

公开(公告)日：2000-02-18

申请号：JP19889599

申请日：1999-07-13

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE ,  GUELEN JOS ,  LUNARDI GENEVIEVE ,  BANVILLET HENRI ,  OBERLIN JEAN-CLAUDE ,  MADDALON CATHERINE

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method which has compatibility with the existing CMOS components manufacturing process in manufacturing a capacitor, having little possibility of causing the dielectric breakdown. SOLUTION: A first metal layer is deposited and etched with leaving a region 12, corresponding to a capacitor plate and contact region 13 on the first metal layer, an input layer 15 is deposited between metallization layers, a first opening is formed into an upper part of the capacitor plate 12, a thin insulation layer 17 is deposited, a second opening 20 is formed into an upper part of the contact region, a second metal layer 24 is deposited for completely filling the opening 20, a physical-chemical etching is applied to suppress the outside region of the second metal layer, and a third metal layer is deposited to cause to be left at positions 31, 32 on the third metal layer above the contact region and capacitor region.

公开(公告)号：FR2781603B1

公开(公告)日：2000-10-06

申请号：FR9809437

申请日：1998-07-21

Applicant: ST MICROELECTRONICS SA

Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE ,  GUELEN JOS ,  LUNARDI GENEVIEVE ,  BANVILLET HENRI ,  OBERLIN JEAN CLAUDE ,  MADDALON CATHERINE

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L21/3205 ,  H01L21/8234

Abstract: Process involves depositing and etching metal layer for region (12) corresponding to a capacitance plate and area (13) contacting a higher layer; depositing insulating layer; forming hole above the plate, depositing thin insulating layer; forming 2nd hole above contact zone; depositing 2nd metal layer; etching 2nd metal layer except in hole-filling regions; and depositing 3rd metal layer (31, 32). The 1st and 2nd metal layers are tungsten, and the 3rd metal layer is Al-Cu. The 1st hole has inclined walls, while the 2nd hole has straight walls.

公开(公告)号：FR2781603A1

公开(公告)日：2000-01-28

申请号：FR9809437

申请日：1998-07-21

Applicant: ST MICROELECTRONICS SA

Inventor： GRIS YVON ,  TROILLARD GERMAINE ,  MOURIER JOCELYNE ,  GUELEN JOS ,  LUNARDI GENEVIEVE ,  BANVILLET HENRI ,  OBERLIN JEAN CLAUDE ,  MADDALON CATHERINE

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L21/3205 ,  H01L21/8234

Abstract: Process involves depositing and etching metal layer for region (12) corresponding to a capacitance plate and area (13) contacting a higher layer; depositing insulating layer; forming hole above the plate, depositing thin insulating layer; forming 2nd hole above contact zone; depositing 2nd metal layer; etching 2nd metal layer except in hole-filling regions; and depositing 3rd metal layer (31, 32). The 1st and 2nd metal layers are tungsten, and the 3rd metal layer is Al-Cu. The 1st hole has inclined walls, while the 2nd hole has straight walls.

公开(公告)号：FR2780552B1

公开(公告)日：2000-08-25

申请号：FR9808152

申请日：1998-06-26

Applicant: ST MICROELECTRONICS SA

Inventor： PERRIN EMMANUEL ,  ROBERT FREDERIC ,  BANVILLET HENRI ,  LIAUZU LUC

IPC: B24B37/04 ,  B24B49/03 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/66 ,  H01L21/304

Abstract: A process for polishing, on a polishing machine and under defined polishing conditions, the external surface of at least one wafer of integrated circuits comprising a projecting feature covered over the entire surface of the wafer with an external layer of a material, consisting in calculating a main equivalent thickness equal to the main surface density of the projecting feature multiplied by the thickness of the latter; in polishing, under the defined polishing conditions, a reference wafer comprising an external layer of the material, having a uniform thickness and covering the surface of this reference wafer, so as to determine the rate of removal by the polishing machine corresponding to the ratio of the thickness removed to the polishing time elapsed; in calculating a polishing time equal to the ratio of the aforementioned equivalent thickness to the aforementioned rate of removal; in calculating a total equivalent thickness equal to the sum of the main equivalent thickness and of a complementary thickness of preset value; in calculating a polishing time equal to the ratio of this total-equivalent thickness to the aforementioned rate of removal; and in carrying out, under the polishing conditions, the polishing operation on at least one wafer to be polished for a duration which is equal to the aforementioned polishing time or which depends on this time.

公开(公告)号：FR2780552A1

公开(公告)日：1999-12-31

申请号：FR9808152

申请日：1998-06-26

Applicant: ST MICROELECTRONICS SA

Inventor： PERRIN EMMANUEL ,  ROBERT FREDERIC ,  BANVILLET HENRI ,  LIAUZU LUC

IPC: B24B37/04 ,  B24B49/03 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/66 ,  H01L21/304

Abstract: The control process involves calculation of equivalent thickness equal to the product of primary surface density (Dsp) and height (Hi) from the basic surface (10) of embedded metallic pattern (11). Attack velocity (V) is determined from removed thickness and polishing time for a reference chip, a calculation of polishing time from the equivalent thickness and the velocity, and control of process by obtained time or a function of it. The process may include a calculation of equivalent thickness complemented by a predetermined value, a calculation of the polishing time and the total equivalent thickness and velocity, and the control of process by the corrected polishing time or a function of it. The control of polishing process may include a measuring of remaining thickness, a subtraction of desired thickness to obtain a correction, a calculation of total equivalent thickness and the corrected polishing time. The process may also include a determination of secondary surface density (Dss), a calculation of the thickness correction and the total equivalent thickness, and a calculation of polishing time. The complemented thickness (Hs) may be obtained by measuring the recovered material (12) and subtracting the height of pattern (Hi) and the desired thickness (Ho), or by measuring the recovered material thickness (Hd) and subtracting the height of pattern (Hi).