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    Circuit for detecting start, circuit for detecting stop, and circuit for detecting data transmitted according to the Inter Integrated Circuit (IIC) protocol
    1.
    发明专利
    Circuit for detecting start, circuit for detecting stop, and circuit for detecting data transmitted according to the Inter Integrated Circuit (IIC) protocol 未知

    公开(公告)号：FR2839827A1

    公开(公告)日：2003-11-21

    申请号：FR0205880

    申请日：2002-05-14

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

    Inventor： MUSUMECI ORAZIO ,  KARI AHMED

    IPC: H03K5/1252 ,  H03K5/19 ,  H04L7/04 ,  H03K5/1534

    Abstract: The circuits for detecting start and stop, respectively, detect the conditions for start and stop on a data signal (SDA) associated with a clock signal (SCL) according to teh IIC protocol. The circuit for detecting start comprises a counter (30) for counting the pulses of a reference clock signal (CLK) when an initialization (reset) signal (RST) is produced by a first detector (20) of a falling front (trailing edge) of the data signal (SDA) and producing a validation signal (COUNT) when the number of counted pulses reaches a predefined number (NB); and a second detector (40) for storing in memory the validation signal (COUNT) when a falling front of the clock signal (SCL) is detected. The circuit (claimed) for detecting start comprises the first detector (20) containing a bistable whose data input is connected to the ground, whose clock input receives the data signal (SDA), and whose output delivers the initialization signal (RST). The second detector (40) contains a bistable whose data input receives the validation signal (COUNT), whose clock input receives the clock signal (SCL), and whose output delivers the start signal (START). The circuit comprises a supplementary initialization circuit for producing a second initialization signal equal to the inverse of the clock signal (SCL) and synchronized on the reference clock signal (CLK), where the second signal is used to initialize the first and/or the second detector (20,40). The circuit (claimed) for detecting stop comprises a detector for producing a stop signal (STOP) when a rising front (leading edge) of the data signal (SDA) is detected after the detection of a rising front of the clock signal (SCL). The detector comprises a bistable whose data input receives a supply voltage, whose clock input receives the data signal (SDA), and whose output delivers the stop signal (STOP). The circuit (claimed) for detecting the data transmitted according to the IIC protocol comprises the circuit for detecting start and the circuit for detecting stop.

    2.
    发明专利
    未知

    公开(公告)号：FR2839827B1

    公开(公告)日：2005-07-15

    申请号：FR0205880

    申请日：2002-05-14

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

    Inventor： MUSUMECI ORAZIO ,  KARI AHMED

    IPC: H03K5/1252 ,  H03K5/19 ,  H04L7/04 ,  H03K5/1534

    Abstract: The circuits for detecting start and stop, respectively, detect the conditions for start and stop on a data signal (SDA) associated with a clock signal (SCL) according to teh IIC protocol. The circuit for detecting start comprises a counter (30) for counting the pulses of a reference clock signal (CLK) when an initialization (reset) signal (RST) is produced by a first detector (20) of a falling front (trailing edge) of the data signal (SDA) and producing a validation signal (COUNT) when the number of counted pulses reaches a predefined number (NB); and a second detector (40) for storing in memory the validation signal (COUNT) when a falling front of the clock signal (SCL) is detected. The circuit (claimed) for detecting start comprises the first detector (20) containing a bistable whose data input is connected to the ground, whose clock input receives the data signal (SDA), and whose output delivers the initialization signal (RST). The second detector (40) contains a bistable whose data input receives the validation signal (COUNT), whose clock input receives the clock signal (SCL), and whose output delivers the start signal (START). The circuit comprises a supplementary initialization circuit for producing a second initialization signal equal to the inverse of the clock signal (SCL) and synchronized on the reference clock signal (CLK), where the second signal is used to initialize the first and/or the second detector (20,40). The circuit (claimed) for detecting stop comprises a detector for producing a stop signal (STOP) when a rising front (leading edge) of the data signal (SDA) is detected after the detection of a rising front of the clock signal (SCL). The detector comprises a bistable whose data input receives a supply voltage, whose clock input receives the data signal (SDA), and whose output delivers the stop signal (STOP). The circuit (claimed) for detecting the data transmitted according to the IIC protocol comprises the circuit for detecting start and the circuit for detecting stop.

    METHOD OF CONFIGURING A MEMORY SPACE THAT IS DIVIDED INTO MEMORY AREAS
    3.
    发明申请
    METHOD OF CONFIGURING A MEMORY SPACE THAT IS DIVIDED INTO MEMORY AREAS 审中-公开
    配置一个划分为记忆区域的存储空间的方法

    公开(公告)号：WO2007023213A3

    公开(公告)日：2007-04-12

    申请号：PCT/FR2006001768

    申请日：2006-07-19

    Applicant: ST MICROELECTRONICS SA ,  MOREAUX CHRISTOPHE ,  KARI AHMED ,  NAURA DAVID ,  RIZZO PIERRE

    Inventor： MOREAUX CHRISTOPHE ,  KARI AHMED ,  NAURA DAVID ,  RIZZO PIERRE

    IPC: G06F12/02

    CPC classification number: G06F12/0292

    Abstract: The invention relates to a method of configuring a memory space (MEM), comprising the following steps consisting in: reading a configuration datum (SZ3) in the memory space (MEM) and dividing at least part of the memory space into memory areas (Z1-Z4) as a function of the configuration datum read; and assigning each memory area with an access number (NBK) that is used to access a datum location in the memory area, together with a logical address of the location in the memory area. The invention is suitable for RFID chips.

    Abstract translation: 本发明涉及一种配置存储空间（MEM）的方法，包括以下步骤：读取存储空间（MEM）中的配置数据（SZ3），并将至少部分存储空间划分为存储区域（Z1 -Z4）作为配置数据读取的函数; 以及为每个存储区域分配用于访问存储区域中的数据位置的访问号码（NBK）以及存储区域中的位置的逻辑地址。 本发明适用于RFID芯片。

    4.
    发明专利
    未知

    公开(公告)号：DE602005002223D1

    公开(公告)日：2007-10-11

    申请号：DE602005002223

    申请日：2005-10-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： KARI AHMED ,  NAURA DAVID

    IPC: H04L25/49 ,  H04L7/02

    Abstract: The method involves generating a edge detection signal (FD) from an encoded data signal (CD) and sampling four pulses of the edge detection signal in a manner to obtain a decoded binary data signal (BD). A binary clock signal (CLK) is generated from the detection signal, where the clock signal is synchronous with the encoded data signal, for changing a logic state of the pulses of the detection signal. An independent claim is also included for a device for decoding a binary encoded data signal and generating a clock signal synchronous with the encoded data signal.

    PROCEDE D'ECRITURE PAR BLOC DANS UNE MEMOIRE
    5.
    发明专利
    PROCEDE D'ECRITURE PAR BLOC DANS UNE MEMOIRE 未知

    公开(公告)号：FR2891653A1

    公开(公告)日：2007-04-06

    申请号：FR0510158

    申请日：2005-10-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： KARI AHMED ,  MOREAUX CHRISTOPHE ,  NAURA DAVID ,  RIZZO PIERRE

    IPC: G11C16/10 ,  G06K7/08 ,  G06K19/073

    Abstract: L'invention concerne un procédé d'écriture par bloc dans une mémoire non volatile programmable électriquement, un bloc à écrire dans la mémoire comprenant au moins un mot. Selon l'invention, le procédé comprend des étapes de détermination d'une durée d'écriture d'un mot en divisant une durée fixée d'écriture d'un bloc par le nombre de mots du bloc à écrire, et de commande de la mémoire pour écrire successivement chaque mot (D) dans la mémoire pendant la durée d'écriture.

    7.
    发明专利
    未知

    公开(公告)号：DE602006000534T2

    公开(公告)日：2009-02-19

    申请号：DE602006000534

    申请日：2006-08-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： NAURA DAVID ,  KARI AHMED ,  MOREAUX CHRISTOPHE ,  RIZZO PIERRE

    IPC: G11C16/22

    Abstract: The circuit has a memory (MEM1) containing transaction data, with electrically erasable and programmable memory cells (C i, j) arranged in horizontal and vertical lines, and linked to word lines (WL i) and bit lines (BL j). A control unit (CTU) executes commands for reading or writing in the memory. The CTU is blocked when reference memory cells of one of the groups contain bits of equal value and if the value is different from a value expected for the one of the groups. The CTU controls a voltage generator (VGEN) which supplies a read voltage (Vread) and an erase-programming voltage (Vpp). An independent claim is also included for a method for protecting an integrated circuit against a global data erasure.

    8.
    发明专利
    未知

    公开(公告)号：DE602006000534D1

    公开(公告)日：2008-03-27

    申请号：DE602006000534

    申请日：2006-08-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： NAURA DAVID ,  KARI AHMED ,  MOREAUX CHRISTOPHE ,  RIZZO PIERRE

    IPC: G11C16/22

    Abstract: The circuit has a memory (MEM1) containing transaction data, with electrically erasable and programmable memory cells (C i, j) arranged in horizontal and vertical lines, and linked to word lines (WL i) and bit lines (BL j). A control unit (CTU) executes commands for reading or writing in the memory. The CTU is blocked when reference memory cells of one of the groups contain bits of equal value and if the value is different from a value expected for the one of the groups. The CTU controls a voltage generator (VGEN) which supplies a read voltage (Vread) and an erase-programming voltage (Vpp). An independent claim is also included for a method for protecting an integrated circuit against a global data erasure.

    PROCEDE ET DISPOSITIF DE VERIFICATION DE L'EXECUTION D'UNE COMMANDE D'ECRITURE DANS UNE MEMOIRE
    9.
    发明专利
    PROCEDE ET DISPOSITIF DE VERIFICATION DE L'EXECUTION D'UNE COMMANDE D'ECRITURE DANS UNE MEMOIRE 未知

    公开(公告)号：FR2894710A1

    公开(公告)日：2007-06-15

    申请号：FR0512631

    申请日：2005-12-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： KARI AHMED ,  MOREAUX CHRISTOPHE ,  NAURA DAVID ,  RIZZO PIERRE

    IPC: G11C29/52 ,  G11C7/24

    Abstract: L'invention concerne un procédé d'exécution d'une commande d'écriture d'un mot binaire dans une mémoire programmable, comprenant des étapes d'écriture de chacun des bits (RB) dans un état programmé d'un mot binaire à écrire (D) dans une cellule mémoire correspondante de la mémoire, de lecture de chaque bit (MB) du mot écrit dans la mémoire (MEM) correspondant à un bit (RB) à l'état programmé du mot à écrire, de comparaison de chaque bit (RB) à l'état programmé du mot à écrire à un bit correspondant (MB) lu dans la mémoire, et de génération d'un signal d'erreur (ER) si au moins un bit du mot à écrire à l'état programmé est différent du bit correspondant lu. Application de l'invention notamment aux circuits intégrés pour carte à puce.

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