公开(公告)号：ITTO20021118A1

公开(公告)日：2004-06-25

申请号：ITTO20021118

申请日：2002-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CAIMI CARLO ,  CONTIN VALENTINA TESSA ,  MERLANI DAVIDE

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51

公开(公告)号：ITMI20121059A1

公开(公告)日：2013-12-19

申请号：ITMI20121059

申请日：2012-06-18

Applicant: ST MICROELECTRONICS SRL

Inventor： BRIVIO MATTEO ,  CAIMI CARLO ,  ROSSI GIORGIO

公开(公告)号：ITMI20112247A1

公开(公告)日：2013-06-14

申请号：ITMI20112247

申请日：2011-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： CAIMI CARLO ,  MASTROMATTEO UBALDO ,  MASTROROSA STEFANO ANTONIO

公开(公告)号：DE60334188D1

公开(公告)日：2010-10-28

申请号：DE60334188

申请日：2003-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIN VALENTINA TESSA ,  CAIMI CARLO ,  MERLANI DAVIDE ,  CAPRARA PAOLO

IPC: H01L27/115 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/423 ,  H01L29/76

公开(公告)号：ITMI20042374A1

公开(公告)日：2005-03-14

申请号：ITMI20042374

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CAIMI CARLO ,  KHOURI OSAMA ,  MASTRODOMENICO GIOVANNI

公开(公告)号：ITTO20021119A1

公开(公告)日：2004-06-25

申请号：ITTO20021119

申请日：2002-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CAIMI CARLO ,  CAPRARA PAOLO ,  CONTIN VALENTINA TESSA ,  MERLANI DAVIDE

IPC: H01L20060101 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76

公开(公告)号：DE602005017461D1

公开(公告)日：2009-12-17

申请号：DE602005017461

申请日：2005-12-14

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  CAIMI CARLO ,  MASTRODOMENICO GIOVANNI ,  CAPRARA PAOLO

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

公开(公告)号：DE602005017113D1

公开(公告)日：2009-11-26

申请号：DE602005017113

申请日：2005-12-14

Applicant: ST MICROELECTRONICS SRL

Inventor： KHOURI OSAMA ,  CAIMI CARLO ,  MASTRODOMENICO GIOVANNI

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

Abstract: Flash NAND memory electronic device comprising non-volatile cells and having a high integration density and relative programming method. Memory device (1) of the type integrated on a semiconductor substrate (3) and comprising one matrix (6) with rows or Word lines (4) and columns or Bit lines (5) organised in sectors (7) of memory cells (2). The device (1) comprising between said cells (2) of said opposite Word lines (4) belonging to at least one of said sectors (7) of said matrix (6) a lateral coating (15) along the direction of the Bit lines (5) having at least one conductive layer (16) with a contact terminal (9) being selectively biased or floating during each program, read or erase operation, each cell belonging to said sector (7).

公开(公告)号：ITMI20042373A1

公开(公告)日：2005-03-14

申请号：ITMI20042373

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CAIMI CARLO ,  CAPRARA PAOLO ,  KHOURI OSAMA ,  MASTRODOMENICO GIOVANNI