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1.发明专利
公开(公告)号：JP2001285027A
公开(公告)日：2001-10-12
申请号：JP2001040561
申请日：2001-02-16
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: PROBLEM TO BE SOLVED: To obtain a feedforward type circuit structure, having programmable zero which composes a time-continual filter, a delaychain, etc. SOLUTION: A couple of amplification cells (14, 15) are connected to each other at a node A and connected between a 1st signal (Vin) input IN of a 1st cell 14 and an output terminal U of a 2nd cell 15, and each cell is equipped with a couple of transistors (10, 2; 6, 7) which have a common conduction terminal and other conduction terminals coupled with a 1st voltage reference Vcc through respective bias members. Furthermore, a node X of the 1st cell 14 is connected to the output terminal U and a transistor 8 has a control terminal connected to a node X of the 1st cell 14, a 1st conduction terminal connected to an output terminal U, and a 2nd conduction terminal coupled with a 2nd voltage reference GND through a capacitor Cc. The transistor 8 is equipped with a circuit leg 13.
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公开(公告)号：JPH06326536A
公开(公告)日：1994-11-25
申请号：JP9365394
申请日：1994-04-06
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , MOLONEY DAVID , PORTALURI SALVATORE
Abstract: PURPOSE: To provide a variable gain amplifier provided with high dynamic characteristics and a wide frequency band, operated by a low voltage combining output signals which are generated by first and second amplifiers and a variable current oscillator and converting them by a converter. CONSTITUTION: This variable gain amplifier VGA is composed of a first voltage- current (V/I) amplifier, provided with a fixed gain and a second V/I amplifier provided with a variable gain operated in parallel with a first amplifier. Then, the output currents of the first and second amplifiers are totaled in a circuit for totaling and third current signals generated by the variable current oscillator driven by a control voltage VCONTROL are totaled as well. Then, the circuit Σfor totaling is used among three circuit blocks and a current-voltage converter (I/V) and supplies a low impedance node for totaling the output currents. Thus, the I/V converter converts the total of the output current signals of the three blocks into voltage signals.
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公开(公告)号：JP2000013185A
公开(公告)日：2000-01-14
申请号：JP13422999
申请日：1999-05-14
Applicant: ST MICROELECTRONICS SRL
Inventor： DE MICHELI MARCO , PORTALURI SALVATORE , BOLLATI GIACOMINO , BRUCCOLERI MELCHIORRE
Abstract: PROBLEM TO BE SOLVED: To shorten transconductance stable time after a request for changing the interruption frequency of a filter by installing a feedback loop between the output/input of a transconductor connected to DAC so that reference current is set and making reference current which is set by DAC into a mirror image. SOLUTION: In a master section circuit, output current IR from DAC 7, which is set by reference current generated by a current source 8 and digital word FC-WORD, is made into a mirror image by a PMOS transistor 20 which is diode-connected. Current which is made into the mirror image is sent later from a PMOS transistor 21 to an NMOS transistor 22. It is made into the mirror image in an NMOS transistor 23. The drain terminal of the transistor 23 is connected to a node 6 and a capacitor 5 is connected to the node 6. Thus, the transistor 22 sets the current of the transistor 23.
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4.发明专利
公开(公告)号：JPH11249708A
公开(公告)日：1999-09-17
申请号：JP36474598
申请日：1998-12-22
Applicant: ST MICROELECTRONICS SRL
Inventor： PORTALURI SALVATORE , PISATI VALERIO
Abstract: PROBLEM TO BE SOLVED: To provide a feed forward(FF) circuit structure with which delay can be programmed according to a request while maintaining the suitable band width of signals. SOLUTION: This FF circuit structure provided with programmable zero is provided with first and second cells to be cascade connected. The said first and second cells are respectively provided with the first and second pairs of bipolar transistors, a first high impedance element, a second high element and a fifth transistor 8. The base terminal of the fifth transistor 8 receives a signal, which is outputted from the collector terminal of the first pair of first transistors 1, to be outputted as a positive code at the first cell but to be outputted as a negative code at the second cell in order to determine a transmission function having a pair of special points in molecules. A second transistor 2 in the said pair of first and second transistors 1 and 2 is controlled by respective third and fourth current sources 11 and 9 having different values.
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公开(公告)号：JPH0773140A
公开(公告)日：1995-03-17
申请号：JP5280994
申请日：1994-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor： ALINI ROBERTO , MOLONEY DAVID , GORNATI SILVANO , PORTALURI SALVATORE
Abstract: PURPOSE: To reduce the integration area and to accelerate the processing concerning a structure provided with a serial type interface for connection to a data transmission line, by connecting a part of a register to the bundled line and transmitting both a register address and data. CONSTITUTION: A decoded address latch 5 stores the output state of an address decoder 4 until the other address is transmitted through a multiplex bus 2. Only when this address is the address of a designated data register 1, according to the output of this latch 5, data transmitted after this address are written in this register. A write line 9 transmits a data write signal through a logic gate 7 of AND type. A data read circuit means 3 reads data out of this register 1 so as to repeat data from the multiplex bus 2. Only when the transmitted address is as prescribed, a read command starts reading from this register 1.
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Patent Agency Ranking
公开(公告)号：DE60103691D1
公开(公告)日：2004-07-15
申请号：DE60103691
申请日：2001-01-15
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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公开(公告)号：IT1309712B1
公开(公告)日：2002-01-30
申请号：ITMI990350
申请日：1999-02-19
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , MARCHESE STEFANO , SAVO ALESSANDRO
IPC: H03G1/00
Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations, comprising a differential input stage which is biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors, characterized in that it comprises two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.
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公开(公告)号：DE69519663T2
公开(公告)日：2001-04-26
申请号：DE69519663
申请日：1995-03-07
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , VAI GIANFRANCO , PORTALURI SALVATORE , DEMICHELI MARCO
Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.
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公开(公告)号：DE69323483D1
公开(公告)日：1999-03-25
申请号：DE69323483
申请日：1993-04-06
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , MOLONEY DAVID , PORTALURI SALVATORE
Abstract: A variable gain amplifier is composed of a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.
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公开(公告)号：IT1316690B1
公开(公告)日：2003-04-24
申请号：ITMI20000393
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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