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公开(公告)号：DE69524220T2
公开(公告)日：2002-07-11
申请号：DE69524220
申请日：1995-09-27
Applicant: ST MICROELECTRONICS SRL
Inventor： COLLI GIANLUCA
IPC: G06G7/163
Abstract: A multiplier (1) presenting four multiplying branches (2-5), each formed by a buffer transistor (21, 31, 41, 51) and by two input transistors (22, 23; 32, 33; 42, 43; 52, 53) arranged in series to one another and connected between two output nodes (12, 13) and a common node (65). A biasing branch (6) presents a diode-connected forcing transistor (61) with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node (65). The forcing transistor (61) forces the input transistors (22, 23; 32, 33; 42, 43; 52, 53) to operate in the triode (linear) region, i.e. as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.
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公开(公告)号：DE69525535D1
公开(公告)日：2002-03-28
申请号：DE69525535
申请日：1995-11-21
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI ALFREDO , COLLI GIANLUCA , CHIOFFI ERNESTINA , GERNA DANILO
Abstract: An efficient adaptivity to varying conditions of luminance is embodied in an optical sensor composed of an array of photosensitive cells each including a photosensitive structure, a storage capacitance, a first switch (CKSTORE) for storing the photogenerated charge in the capacitance, and a second switch (CKREAD) for selecting the capacitance when reading the charge stored therein, by detecting the level of the global current photogenerated by the totality of the photosensitive elements, during an initial phase of each frame capture, storage and reading cycle, and by subsequently controlling the closing interval of said first switch (CKSTORE) of the cells in function of the detected level of the global photogenerated current. The implementing control circuit may be realized in various forms.
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公开(公告)号：DE69524220D1
公开(公告)日：2002-01-10
申请号：DE69524220
申请日：1995-09-27
Applicant: ST MICROELECTRONICS SRL
Inventor： COLLI GIANLUCA
IPC: G06G7/163
Abstract: A multiplier (1) presenting four multiplying branches (2-5), each formed by a buffer transistor (21, 31, 41, 51) and by two input transistors (22, 23; 32, 33; 42, 43; 52, 53) arranged in series to one another and connected between two output nodes (12, 13) and a common node (65). A biasing branch (6) presents a diode-connected forcing transistor (61) with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node (65). The forcing transistor (61) forces the input transistors (22, 23; 32, 33; 42, 43; 52, 53) to operate in the triode (linear) region, i.e. as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.
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Patent Agency Ranking
公开(公告)号：DE69518326T2
公开(公告)日：2001-01-18
申请号：DE69518326
申请日：1995-10-13
Applicant: ST MICROELECTRONICS SRL
Inventor： FABBRIZIO VITO , COLLI GIANLUCA , KRAMER ALAN
Abstract: A neural network (1) including a number of synaptic weighting elements (15, 17), and a neuron stage (5); each of the synaptic weighting elements (15, 17) having a respective synaptic input connection (11, 13) supplied with a respective input signal (x1, ..., xn); and the neuron stage (5) having inputs (36, 37) connected to the synaptic weighting elements, and being connected to an output (39) of the neural network (1) supplying a digital output signal (O). The synaptic weighting elements (15, 17) are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage (5) provides for measuring conductance (33-35, 43-45) on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
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公开(公告)号：DE69507033T2
公开(公告)日：1999-05-12
申请号：DE69507033
申请日：1995-10-09
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI ALFREDO , COLLI GIANLUCA , CHIOFFI ERNESTINA
Abstract: The absorption of current from the supply rails by a current comparator circuit producing a logic configuration of two complementary nodes of a first branch and of a second branch, respectively, in function of the comparison between a first current forced through the first branch and a second current forced through the second branch is limited by discriminating the lowest between the two compared currents and by mirroring the discriminated lowest current on the circuit branch through which the highest current is being forced. The comparator circuit comprises means that are responsive to the logic configuration of the two complementary nodes of the comparator circuit so as to assume a state capable of configuring the circuit to function as a current mirror that forces the lowest current on the other branch of the current comparator circuit.
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公开(公告)号：DE69507033D1
公开(公告)日：1999-02-11
申请号：DE69507033
申请日：1995-10-09
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI ALFREDO , COLLI GIANLUCA , CHIOFFI ERNESTINA
Abstract: The absorption of current from the supply rails by a current comparator circuit producing a logic configuration of two complementary nodes of a first branch and of a second branch, respectively, in function of the comparison between a first current forced through the first branch and a second current forced through the second branch is limited by discriminating the lowest between the two compared currents and by mirroring the discriminated lowest current on the circuit branch through which the highest current is being forced. The comparator circuit comprises means that are responsive to the logic configuration of the two complementary nodes of the comparator circuit so as to assume a state capable of configuring the circuit to function as a current mirror that forces the lowest current on the other branch of the current comparator circuit.
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公开(公告)号：DE69525535T2
公开(公告)日：2002-11-28
申请号：DE69525535
申请日：1995-11-21
Applicant: ST MICROELECTRONICS SRL
Inventor： TOMASINI ALFREDO , COLLI GIANLUCA , CHIOFFI ERNESTINA , GERNA DANILO
Abstract: An efficient adaptivity to varying conditions of luminance is embodied in an optical sensor composed of an array of photosensitive cells each including a photosensitive structure, a storage capacitance, a first switch (CKSTORE) for storing the photogenerated charge in the capacitance, and a second switch (CKREAD) for selecting the capacitance when reading the charge stored therein, by detecting the level of the global current photogenerated by the totality of the photosensitive elements, during an initial phase of each frame capture, storage and reading cycle, and by subsequently controlling the closing interval of said first switch (CKSTORE) of the cells in function of the detected level of the global photogenerated current. The implementing control circuit may be realized in various forms.
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公开(公告)号：DE69518326D1
公开(公告)日：2000-09-14
申请号：DE69518326
申请日：1995-10-13
Applicant: ST MICROELECTRONICS SRL
Inventor： FABBRIZIO VITO , COLLI GIANLUCA , KRAMER ALAN
Abstract: A neural network (1) including a number of synaptic weighting elements (15, 17), and a neuron stage (5); each of the synaptic weighting elements (15, 17) having a respective synaptic input connection (11, 13) supplied with a respective input signal (x1, ..., xn); and the neuron stage (5) having inputs (36, 37) connected to the synaptic weighting elements, and being connected to an output (39) of the neural network (1) supplying a digital output signal (O). The synaptic weighting elements (15, 17) are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage (5) provides for measuring conductance (33-35, 43-45) on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
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