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公开(公告)号:JP2002319293A
公开(公告)日:2002-10-31
申请号:JP2002107937
申请日:2002-04-10
Applicant: ST MICROELECTRONICS SRL
Inventor: GREGORI STEFANO , MICHELONI RINO , PIERIN ANDREA , KHOURI OSAMA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To realize a method for speedily and highly precisely programming a memory cell. SOLUTION: In the method for programming a non-volatile memory cell 1, at least first and second programming pulse trains F1, F2 having pulse width increasing in stages are applied continuously to a control terminal 2 of the memory cell 1, but amplitude increment between a pulse in the first programming train F1 and the next one is made larger than the amplitude increment between a pulse in the second programming train F2 and the next one. Advantageously, third programming pulse trains F0, F3, having pulse width which increases in stages, are applied to the control terminal 2 of the memory cell 1 before the first programming pulse train F1, but amplitude increment between a pulse and the next one is made smaller than the amplitude increment in the first programming train F1, and is substantially equal to the amplitude increment in the second programming train F2 or larger than the amplitude increment in the first programming train F1.
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公开(公告)号:ITMI20001585A1
公开(公告)日:2002-01-14
申请号:ITMI20001585
申请日:2000-07-13
Applicant: ST MICROELECTRONICS SRL
Inventor: KHOURI OSAMA , TORELLI GUIDO , MICHELONI RINO , PIERIN ANDREA , GREGORI STEFANO , SANGALLI MIRIAM
IPC: G11C16/08
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公开(公告)号:ITTO20001049A1
公开(公告)日:2002-05-07
申请号:ITTO20001049
申请日:2000-11-07
Applicant: ST MICROELECTRONICS SRL
Inventor: MICHELONI RINO , GREGORI STEFANO , FERRARI PIETRO
IPC: H03M13/00
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公开(公告)号:ITTO20001049D0
公开(公告)日:2000-11-07
申请号:ITTO20001049
申请日:2000-11-07
Applicant: ST MICROELECTRONICS SRL
Inventor: TORELLI GUIDO , GREGORI STEFANO , FERRARI PIETRO
IPC: H03M13/00
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公开(公告)号:ITMI20001585D0
公开(公告)日:2000-07-13
申请号:ITMI20001585
申请日:2000-07-13
Applicant: ST MICROELECTRONICS SRL
Inventor: KHOURI OSAMA , TORELLI GUIDO , MICHELONI RINO , PIERIN ANDREA , GREGORI STEFANO , SANGALLI MIRIAM
IPC: G11C16/08
Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.
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公开(公告)号:DE60139670D1
公开(公告)日:2009-10-08
申请号:DE60139670
申请日:2001-04-10
Applicant: ST MICROELECTRONICS SRL
Inventor: GREGORI STEFANO , MICHELONI RINO , PIERIN ANDREA , KHOURI OSAMA , TORELLI GUIDO
Abstract: The method involves applying in succession, to a control terminal of the memory cell, at least two programming pulse trains (F1,F2) with pulse amplitude increasing in staircase fashion. The amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Transition from the first programming pulse to train to the second is made when the memory cell has a threshold voltage with a pre-set relation with a reference value.
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公开(公告)号:DE60031860D1
公开(公告)日:2006-12-28
申请号:DE60031860
申请日:2000-11-23
Applicant: ST MICROELECTRONICS SRL
Inventor: MICHELONI RINO , KHOURI OSAMA , PIERIN ANDREA , GREGORI STEFANO , TORELLI GUIDO
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公开(公告)号:IT1320699B1
公开(公告)日:2003-12-10
申请号:ITTO20000936
申请日:2000-10-06
Applicant: ST MICROELECTRONICS SRL
Inventor: MICHELONI RINO , GREGORI STEFANO , KHOURI OSAMA , TORELLI GUIDO
Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).
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公开(公告)号:ITTO20000936A1
公开(公告)日:2002-04-08
申请号:ITTO20000936
申请日:2000-10-06
Applicant: ST MICROELECTRONICS SRL
Inventor: TORELLI GUIDO , MICHELONI RINO , PIERIN ANDREA , GREGORI STEFANO , KHOURI OSAMA
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公开(公告)号:ITTO20000936D0
公开(公告)日:2000-10-06
申请号:ITTO20000936
申请日:2000-10-06
Applicant: ST MICROELECTRONICS SRL
Inventor: TORELLI GUIDO , MICHELONI RINO , PIERIN ANDREA , GREGORI STEFANO , KHOURI OSAMA
Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).
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