公开(公告)号：DE60214868D1

公开(公告)日：2006-11-02

申请号：DE60214868

申请日：2002-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  GIAMBARTINO ANTONIO ,  LA MALFA ANTONINO ,  POLIZZI SALVATORE

IPC: G11C16/10 ,  G11C16/12

Abstract: The invention relates to a circuit architecture and a method for performing a page programming in non volatile memory electronic devices equipped with a memory cell matrix (3) and an SPI serial communication interface (2), as well as circuit portions associated to the cell matrix (3) and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank (5) is provided to store and draw data during the page programming in the pseudo-serial mode through said interface (2). Data latching is performed one bit at a time and the following data retrieval occurs instead with at least two bytes at a time.

公开(公告)号：ITTO20030115A1

公开(公告)日：2004-08-18

申请号：ITTO20030115

申请日：2003-02-17

Applicant: ST MICROELECTRONICS SRL

Inventor： LA MALFA ANTONINO ,  MESSINA MARCO

IPC: G06F20060101 ,  G11C16/12

公开(公告)号：ITMI20021583A1

公开(公告)日：2004-01-19

申请号：ITMI20021583

申请日：2002-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  LA MALFA ANTONINO

IPC: G06F12/00 ,  G06F12/06 ,  G11C8/06 ,  G11C15/00

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

公开(公告)号：ITVA20050002A1

公开(公告)日：2006-07-21

申请号：ITVA20050002

申请日：2005-01-20

Applicant: ST MICROELECTRONICS SRL

Inventor： LA MALFA ANTONINO ,  MESSINA MARCO

公开(公告)号：ITVA20010033A1

公开(公告)日：2003-04-14

申请号：ITVA20010033

申请日：2001-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： MESSINA MARCO ,  LA MALFA ANTONINO

IPC: H03B29/00 ,  H03K3/84

Abstract: A random-bit sequence generator includes a biasing circuit, a source of a noisy voltage signal biased by the biasing circuit, an amplification stage generating an amplified signal representative of the sole non-zero-frequency (AC) component of the noisy voltage signal and an output stage electrically in cascade to the amplification stage that generates a random bit sequence in function of the amplified signal. The generator also filters the undesired low-frequency disturbance components because the amplification stage comprises an input low-pass filter that feeds the zero- (DC) component of the noisy voltage signal to one of the inputs of a differential amplifier, to another input of which is fed the non-filtered noisy voltage signal.