公开(公告)号：DE60214868D1

公开(公告)日：2006-11-02

申请号：DE60214868

申请日：2002-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  GIAMBARTINO ANTONIO ,  LA MALFA ANTONINO ,  POLIZZI SALVATORE

IPC: G11C16/10 ,  G11C16/12

Abstract: The invention relates to a circuit architecture and a method for performing a page programming in non volatile memory electronic devices equipped with a memory cell matrix (3) and an SPI serial communication interface (2), as well as circuit portions associated to the cell matrix (3) and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank (5) is provided to store and draw data during the page programming in the pseudo-serial mode through said interface (2). Data latching is performed one bit at a time and the following data retrieval occurs instead with at least two bytes at a time.

公开(公告)号：DE60229649D1

公开(公告)日：2008-12-11

申请号：DE60229649

申请日：2002-11-28

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  PERRONI MAURIZIO FRANCESCO ,  SCHILLACI PAOLINO

IPC: G06F13/42 ,  G11C7/10 ,  G11C8/04 ,  G11C16/26

公开(公告)号：ITMI20021583A1

公开(公告)日：2004-01-19

申请号：ITMI20021583

申请日：2002-07-18

Applicant: ST MICROELECTRONICS SRL

Inventor： SCHILLACI PAOLINO ,  POLI SALVATORE ,  LA MALFA ANTONINO

IPC: G06F12/00 ,  G06F12/06 ,  G11C8/06 ,  G11C15/00

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

公开(公告)号：ITMI20032134A1

公开(公告)日：2005-05-07

申请号：ITMI20032134

申请日：2003-11-06

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTAGNA GIUSEPPE ,  PERRONI MAURIZIO FRANCESCO ,  SCHILLACI PAOLINO

IPC: G06K20060101 ,  G11C8/12 ,  G11C11/34 ,  G11C16/08

公开(公告)号：ITMI20041038A1

公开(公告)日：2004-08-25

申请号：ITMI20041038

申请日：2004-05-25

Applicant: ST MICROELECTRONICS SRL

Inventor： MAZZARA SALVATORE ,  PERRONI MAURIZIO FRANCESCO ,  SCHILLACI PAOLINO

IPC: G11C8/00 ,  G11C16/12 ,  G11C16/30

公开(公告)号：ITVA20020016A1

公开(公告)日：2003-08-21

申请号：ITVA20020016

申请日：2002-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  POLI SALVATORE ,  SCHILLACI PAOLINO

IPC: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

公开(公告)号：ITVA20020016D0

公开(公告)日：2002-02-21

申请号：ITVA20020016

申请日：2002-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： POLIZZI SALVATORE ,  POLI SALVATORE ,  SCHILLACI PAOLINO

IPC: G11C16/22

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.