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    2.
    发明专利
    未知

    公开(公告)号：DE69812369T2

    公开(公告)日：2004-02-19

    申请号：DE69812369

    申请日：1998-12-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  OTTINI DANIELE ,  SAVO ALESSANDRO

    IPC: G11B20/10 ,  G11B20/00 ,  H03M1/10 ,  H03M1/12 ,  H04L27/08

    Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

    3.
    发明专利
    未知

    公开(公告)号：DE69812369D1

    公开(公告)日：2003-04-24

    申请号：DE69812369

    申请日：1998-12-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  OTTINI DANIELE ,  SAVO ALESSANDRO

    IPC: G11B20/10 ,  G11B20/00 ,  H03M1/10 ,  H03M1/12 ,  H04L27/08

    Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

    4.
    发明专利
    未知

    公开(公告)号：DE69901781D1

    公开(公告)日：2002-07-18

    申请号：DE69901781

    申请日：1999-03-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  SAVO ALESSANDRO ,  MARCHESE STEFANO

    IPC: H03G1/00

    Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations, comprising a differential input stage which is biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors, characterized in that it comprises two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.

    5.
    发明专利
    未知

    公开(公告)号：IT1309712B1

    公开(公告)日：2002-01-30

    申请号：ITMI990350

    申请日：1999-02-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PISATI VALERIO ,  PORTALURI SALVATORE ,  MARCHESE STEFANO ,  SAVO ALESSANDRO

    IPC: H03G1/00

    Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations, comprising a differential input stage which is biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors, characterized in that it comprises two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.

    6.
    发明专利
    未知

    公开(公告)号：DE69824143D1

    公开(公告)日：2004-07-01

    申请号：DE69824143

    申请日：1998-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARCHESE STEFANO ,  PISATI VALERIO ,  PORTALURI SALVATORE ,  SAVO ALESSANDRO

    IPC: H03G1/00 ,  H03G7/06 ,  H03G3/00 ,  H03G7/00

    Abstract: An amplifier with programmable gain and input linearity, comprising an input stage (10), which is suitable to receive a voltage signal (V , V ) and perform current conversion thereof with compression, and an output stage (30), which is connected to the input stage (10) and is suitable to decompress the signal in output from the input stage, producing gain amplification thereof; the particularity of the amplifier is the fact that it further comprises at least one current amplifier stage (20) which is interposed between the input stage (10) and the output stage (30) and comprises at least one bipolar transistor (21, 22) which is series-connected to a load diode (23, 24) and to a current source (2I2); programmable means (I2, I2*) for reducing the transconductance of the load diode (23, 24) being provided in the at least one amplifier stage (20) to determine a programmable amplification factor for the gain of the amplifier.

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