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    HIGH-FREQUENCY TRACK-AND-HOLD FULL-WAVE RECTIFIER
    1.
    发明专利
    HIGH-FREQUENCY TRACK-AND-HOLD FULL-WAVE RECTIFIER 失效

    公开(公告)号：JP2000166237A

    公开(公告)日：2000-06-16

    申请号：JP11667499

    申请日：1999-04-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  OTTINI DANIELE ,  DEMICHELI MARCO ,  BOLLATI GIACOMINO

    IPC: H02M7/02 ,  G01R19/22 ,  H02M7/12 ,  H03F3/45

    Abstract: PROBLEM TO BE SOLVED: To reduce higher harmonics and dynamic distortion by receiving a differential logical synchronizing signal at the input terminal of a timing circuit, and supplying the first differential timing signal to a track-and-hold stage and the second differential timing signal to a flip flop, respectively. SOLUTION: Differential logical synchronizing signals Clk+, Clk- are received at the input terminal of a timing circuit, and the first differential timing signals TClK+, TClK- are outputted to a differential track-and-hold stage TandH at an output terminal. The second differential timing signals DClK+, DClK- are outputted to a flip flop LATCH-ECL at the output terminal of the timing circuit. The differential track-and-hold stage TandH tracks differential analog input signals IN+, IN- during the tracking phase of the first differential timing signals TClK+, TClK-. The differential flip flop LaATCH-ECL outputs the third differential logical control signals S+, S-.

    FLASH ANALOG/DIGITAL CONVERTER
    2.
    发明专利
    FLASH ANALOG/DIGITAL CONVERTER 失效

    公开(公告)号：JP2000174626A

    公开(公告)日：2000-06-23

    申请号：JP33007299

    申请日：1999-11-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE ,  BOLLATI GIACOMINO ,  DEMICHELI MARCO

    IPC: H03M1/36 ,  H03M1/08 ,  H03M1/12

    Abstract: PROBLEM TO BE SOLVED: To provide a flash analog/digital converter capable of outputting a temperature measurement digital code. SOLUTION: This flash analog/digital converter is provided with a bank composed of comparators (COMPi) provided with differential output for generating a temperature measurement code and 3-input (A, B and C) logical NOR gates (NORj) and is provided with a passive interface respectively composed of the plural pieces of voltage dividers (Ra-Rb) connected between the non- inverted output (out-p) of the respective comparators (COMPi) and the inverted output (out-n) of the comparators (COMPi+1) of the higher order of the bank. The corresponding logical NOR gate (NORj) of the bank is provided with first input (A) connected to the inverted output (out-n) of the respective comparators (COMPi-1), second input (B) connected to the non-inverted output (out-p) of the comparators (COMPi) of the higher order and third input (C) connected to the intermediate tap of the voltage dividers (Ra-Rb).

    4.
    发明专利
    未知

    公开(公告)号：DE69825060D1

    公开(公告)日：2004-08-19

    申请号：DE69825060

    申请日：1998-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOLLATI GIACOMINO ,  ALINI ROBERTO ,  OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE

    IPC: H03H11/04

    Abstract: A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current (iz), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current (iz) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.

    7.
    发明专利
    未知

    公开(公告)号：DE69833932D1

    公开(公告)日：2006-05-11

    申请号：DE69833932

    申请日：1998-04-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  OTTINI DANIELE ,  DEMICHELI MARCO ,  BOLLATI GIACOMINO

    IPC: G01R19/04 ,  H02M7/02 ,  G01R19/22 ,  H02M7/12 ,  H03F3/45

    Abstract: A full-wave rectifier for monitoring the amplitude of a differential analog signal (IN+, IN-) is composed of a differential Track&Hold stage (T&H) controlled by a first differential logic timing signal (TClk+, TClk-), tracking the differential analog input signal (IN+, IN-) during a tracking phase that corresponds to a high logic stage of the first differential timing signal (TClk+, TClk-), producing a differential output signal that is a replica of the input signal and storing it during a successive storing phase that corresponds to a low logic state of the first differential timing signal (TClk+, TClk-); a first differential output amplifier ( @ ) having inputs coupled to the output of the Track&Hold stage (T&H); a differential bistable circuit (LATCH-ECL), controlled by a second differential logic timing signal (DClk+, DClk-), having inputs coupled to the differential outputs of the first amplifier ( @ ) and producing a third differential logic control signal (S+, S-); a second multiplexed amplifier (Analog-Amp @ ), controlled by the third differential control signal (S+, S-), having inputs coupled to the output of the Track&Hold stage (T&H) and outputting a differential analog signal (OUT+, OUT-) of amplitude function of the amplitude of the differential input signal (IN+, IN-); a timing circuit (T @ C @ ) receiving at an input a differential logic synchronism signal (Clk+, Clk-) and generating the first differential timing signal (TClk+, TClk-) of said Track&Hold stage (T&H) and the second differential timing signal (DClk+, DClk-) of said bistable circuit (LATCH-ECL).

    9.
    发明专利
    未知

    公开(公告)号：DE69812369D1

    公开(公告)日：2003-04-24

    申请号：DE69812369

    申请日：1998-12-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  OTTINI DANIELE ,  SAVO ALESSANDRO

    IPC: G11B20/10 ,  G11B20/00 ,  H03M1/10 ,  H03M1/12 ,  H04L27/08

    Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

    10.
    发明专利
    未知

    公开(公告)号：DE69803856D1

    公开(公告)日：2002-03-21

    申请号：DE69803856

    申请日：1998-11-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE ,  BOLLATI GIACOMINO ,  DEMICHELI MARCO

    IPC: H03M1/36 ,  H03M1/08 ,  H03M1/12 ,  H03M7/16

    Abstract: A flash analog-to-digital converter comprising a bank of comparators (COMPi) with a differential output, generating a thermometric code and a bank of three-input (A,B,C) logic NOR gates (NORj) for correcting errors in said thermometric code, has enhanced immunity to noise and reduced imprecisions, especially at high conversion rates upon occurence of metastability within the comparators, by providing for a passive interface constituted by a plurality of voltage dividers (Ra-Rb), each connected between the noninverted output (out_p) of a respective comparator (COMPi) and the inverted output (out_n) of the comparator of higher order (COMPi+1) of said bank; a corresponding logic NOR gate (NORj) of said bank having a first input (A) coupled to the inverted output (out_n) of said respective comparator (COMPi-1), a second input (B) coupled to the noninverted output (out_p) of said comparator (COMPi) of higher order and a third input (C) coupled to an intermediate tap of said voltage divider (Ra-Rb).

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