公开(公告)号：JPH11265588A

公开(公告)日：1999-09-28

申请号：JP36090498

申请日：1998-12-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  ZATELLI NICOLA ,  SOURGEN LAURENT ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable the protection of an EEPROM cell which is improved with respect to abnormal readouts by allowing the cell to include floating-gate transistors, a first metallic layer over-lapping with a semiconductor substrate and a second metallic layer positioned by being more separated from the substrate than the first metallic layer and allowing the metallic first layer to be arranged so as to be overlapped in major portions of floating gate terminals. SOLUTION: A metallic structure for a screen 50 is arrayed so as to be overlapped on floating gate terminals 30 and covers only the terminals 30 completely. Since it is advantageous that the metallic structure 50 is formed in a first metallic layer, a selection terminal is provided by a poly silicon structure contacting in the relation that it is oven lapped with a metallic structure 242 formed in the first metallic layer in order to lower the low efficiency of a word line. Moreover, it is advantageous in order to obtain a small-sized cell layout that one side of readout terminals 14, 16 or both terminals are provided by a metallic structure to be formed in a metallic layer succeeding to the first metallic layer, that is, the second metallic layer.

公开(公告)号：DE69831921D1

公开(公告)日：2006-03-02

申请号：DE69831921

申请日：1998-12-04

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  SOURGEN LAURENT ,  ZATELLI NICOLA ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L23/556 ,  H01L23/58 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792