公开(公告)号：DE69831921D1

公开(公告)日：2006-03-02

申请号：DE69831921

申请日：1998-12-04

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  SOURGEN LAURENT ,  ZATELLI NICOLA ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L23/556 ,  H01L23/58 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH11265588A

公开(公告)日：1999-09-28

申请号：JP36090498

申请日：1998-12-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  ZATELLI NICOLA ,  SOURGEN LAURENT ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable the protection of an EEPROM cell which is improved with respect to abnormal readouts by allowing the cell to include floating-gate transistors, a first metallic layer over-lapping with a semiconductor substrate and a second metallic layer positioned by being more separated from the substrate than the first metallic layer and allowing the metallic first layer to be arranged so as to be overlapped in major portions of floating gate terminals. SOLUTION: A metallic structure for a screen 50 is arrayed so as to be overlapped on floating gate terminals 30 and covers only the terminals 30 completely. Since it is advantageous that the metallic structure 50 is formed in a first metallic layer, a selection terminal is provided by a poly silicon structure contacting in the relation that it is oven lapped with a metallic structure 242 formed in the first metallic layer in order to lower the low efficiency of a word line. Moreover, it is advantageous in order to obtain a small-sized cell layout that one side of readout terminals 14, 16 or both terminals are provided by a metallic structure to be formed in a metallic layer succeeding to the first metallic layer, that is, the second metallic layer.

公开(公告)号：FR2837974A1

公开(公告)日：2003-10-03

申请号：FR0203787

申请日：2002-03-26

Applicant: ST MICROELECTRONICS SA

Inventor： FARGES MICHEL ,  LISART MATHIEU

IPC: G11C16/10 ,  G11C16/02 ,  G11C7/00

Abstract: The electrically programmable memory (MEM2) comprises a memory array (MA) containing the memory cells (CFi,j) connected to the word lines (WLi) and the bit lines (BLj), and means for programming for registering a set of binary words in a row of memory cells (CFim)1 - CFi,x) connected to the same word line, for erasing the memory cells of the row and then applying several programming cycles to the groups of memory cells of the row. Each programming cycle includes an application of the programming voltage (Vpp) to the memory cells which receive a bit equal to the first logic value (1), and the cells receiving a bit equal to the second logic value (0) which is inverse to the first are left in the erased state. The programming voltage is applied to no more than N memory cells at a time. The programming means inclusive of a programming register (PGR2), a mask register (MREG1), a shift register (SREG), an OR-gate with X inputs (ORX), a counter (CMP), and a sequencer (SEQ), are laid out for registering the bits belonging to different words chosen so that the number of memory cells receiving the programming voltage during the programming cycle is maximum but not greater than N. The selected groups of memory cells comprise a variable number of memory cells, and the number of cells receiving the programming voltage is maximum. In the case of registering an integer number of binary words, the integer number is variable and chosen so that the total number of bits equal to the second logic value is maximum. The programming means are arranged for registering a chain of bits comprising N bits equal to the second logic value. The programming mask is combined bit to bit with the bits of words to register, and comprises the bits of logic value authorizing the programming of memory cells, and the bits of logic value forbidding the programming of memory cells.

公开(公告)号：DE69700123D1

公开(公告)日：1999-04-08

申请号：DE69700123

申请日：1997-05-05

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G11C16/12 ,  H03K4/00 ,  G11C16/06

Abstract: The circuit comprises a voltage booster which produces a high DC output. A control circuit uses this to generate a ramped programming voltage. The source of a first P-type load transistor is connected to the output of the voltage booster. Its drain is coupled to a capacitor and by its gate to the control circuit. The high voltage programming output is produced at the transistor drain. The control circuit includes a pulse generator which applies a stepped voltage to the load transistor gate. The capacitor is formed by line of bits in a memory map. The control circuit also comprises a P-type transistor which is mounted in diode configuration and is used to charge the capacitor with a constant current.

公开(公告)号：DE69508207T2

公开(公告)日：1999-10-14

申请号：DE69508207

申请日：1995-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G06F12/14 ,  G06F21/02 ,  G06K17/00

Abstract: The system includes a microprocessor(1), a memory bank(2- 9) containing words(17), a transmission bus(15) for sending data, address and control information between the microprocessor and the memory bank, and an access protection circuit(18). The access protection circuit contains a decision table(18), circuits(19) for addressing the table(18), with the addresses of the memory words. A protection circuit(31-33) which produces a protection signal as a function of a read of the decision table. It allots(14) to certain words to be protected(17) an arrangement of control bits(21) , a circuit(22) to read these control bits at the time (LEC) of reading these words, and a circuit(23-25) to address the decision table as a function of the value of the bits read.

公开(公告)号：DE69700123T2

公开(公告)日：1999-06-24

申请号：DE69700123

申请日：1997-05-05

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G11C16/12 ,  H03K4/00 ,  G11C16/06

Abstract: The circuit comprises a voltage booster which produces a high DC output. A control circuit uses this to generate a ramped programming voltage. The source of a first P-type load transistor is connected to the output of the voltage booster. Its drain is coupled to a capacitor and by its gate to the control circuit. The high voltage programming output is produced at the transistor drain. The control circuit includes a pulse generator which applies a stepped voltage to the load transistor gate. The capacitor is formed by line of bits in a memory map. The control circuit also comprises a P-type transistor which is mounted in diode configuration and is used to charge the capacitor with a constant current.

公开(公告)号：DE602006012765D1

公开(公告)日：2010-04-22

申请号：DE602006012765

申请日：2006-07-12

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  DEMANGE NICOLAS

IPC: G11C7/24 ,  G11C7/10

Abstract: The method involves applying electrical signals (IS0 - ISm) each representing a state of one of selected memory cells to memory cell read circuits supplying a binary output signal representing state of the cell to which it is linked. A rule to allocate the signals to the circuits is modified by applying a permutation to a part of the signals, so that each read circuit processes electrical signals of different ranks during different reading cycles. The rule is randomly or pseudo-randomly modified for every T reading cycles, where T is a constant or a variable integer greater than or equal to 1. An independent claim is also included for a memory comprising memory cells.

公开(公告)号：FR2889349A1

公开(公告)日：2007-02-02

申请号：FR0507912

申请日：2005-07-26

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  DEMANGE NICOLAS

IPC: G11C7/06 ,  G06F12/14 ,  G06K19/07

Abstract: L'invention concerne un procédé de traitement de signaux électriques (ISO-ISm) parallèles, au moyen de circuits de traitement parallèles (CT0-CTm), comprenant des cycles successifs de traitement des signaux électriques selon une règle d'assignation des signaux électriques aux circuits de traitement. Selon l'invention, le procédé comprend, entre les cycles de traitement, une étape de modification de la règle d'assignation des signaux électriques (IS0-ISm) aux circuits de traitement (CT0-CTm), de sorte qu'un circuit de traitement traite des signaux électriques de rangs différents au cours de cycles de traitement différents. Application notamment à la sécurisation d'une mémoire pendant des phases de lecture de la mémoire et d'un circuit intégré à microprocesseur utilisant une telle mémoire.

公开(公告)号：DE69508207D1

公开(公告)日：1999-04-15

申请号：DE69508207

申请日：1995-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G06F12/14 ,  G06F21/02 ,  G06K17/00

Abstract: The system includes a microprocessor(1), a memory bank(2- 9) containing words(17), a transmission bus(15) for sending data, address and control information between the microprocessor and the memory bank, and an access protection circuit(18). The access protection circuit contains a decision table(18), circuits(19) for addressing the table(18), with the addresses of the memory words. A protection circuit(31-33) which produces a protection signal as a function of a read of the decision table. It allots(14) to certain words to be protected(17) an arrangement of control bits(21) , a circuit(22) to read these control bits at the time (LEC) of reading these words, and a circuit(23-25) to address the decision table as a function of the value of the bits read.