公开(公告)号：DE69831921D1

公开(公告)日：2006-03-02

申请号：DE69831921

申请日：1998-12-04

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  SOURGEN LAURENT ,  ZATELLI NICOLA ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L23/556 ,  H01L23/58 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH11265588A

公开(公告)日：1999-09-28

申请号：JP36090498

申请日：1998-12-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  ZATELLI NICOLA ,  SOURGEN LAURENT ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable the protection of an EEPROM cell which is improved with respect to abnormal readouts by allowing the cell to include floating-gate transistors, a first metallic layer over-lapping with a semiconductor substrate and a second metallic layer positioned by being more separated from the substrate than the first metallic layer and allowing the metallic first layer to be arranged so as to be overlapped in major portions of floating gate terminals. SOLUTION: A metallic structure for a screen 50 is arrayed so as to be overlapped on floating gate terminals 30 and covers only the terminals 30 completely. Since it is advantageous that the metallic structure 50 is formed in a first metallic layer, a selection terminal is provided by a poly silicon structure contacting in the relation that it is oven lapped with a metallic structure 242 formed in the first metallic layer in order to lower the low efficiency of a word line. Moreover, it is advantageous in order to obtain a small-sized cell layout that one side of readout terminals 14, 16 or both terminals are provided by a metallic structure to be formed in a metallic layer succeeding to the first metallic layer, that is, the second metallic layer.

公开(公告)号：DE60037248D1

公开(公告)日：2008-01-10

申请号：DE60037248

申请日：2000-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA ,  ATTI MASSIMO ,  PALUMBO ELISABETTA ,  TORELLI COSIMO

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

Abstract: A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

公开(公告)号：ITTO990884D0

公开(公告)日：1999-10-12

申请号：ITTO990884

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA

IPC: G11C16/04

Abstract: A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.

公开(公告)号：ITTO990884A1

公开(公告)日：2001-04-12

申请号：ITTO990884

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA

IPC: G11C16/04

Abstract: A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.

公开(公告)号：IT1301799B1

公开(公告)日：2000-07-07

申请号：ITMI981449

申请日：1998-06-25

Applicant: ST MICROELECTRONICS SRL

Inventor： VAJANA BRUNO ,  PIO FEDERICO ,  ZATELLI NICOLA

IPC: H01L21/8247 ,  H01L27/115

公开(公告)号：ITMI981449A1

公开(公告)日：1999-12-25

申请号：ITMI981449

申请日：1998-06-25

Applicant: ST MICROELECTRONICS SRL

Inventor： CREMONESI CARLO ,  ZATELLI NICOLA ,  PIO FEDERICO

IPC: H01L21/8247 ,  H01L27/115

Abstract: Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch determining in the source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during the third step, and a sixth step of dopant introduction in the regions of active area for the formation of regions of source and drain of the cells. Before the fourth step a selective introduction of dopant is provided in correspondence of regions of the common source lines in which the excavations will be formed, for the formation of doped regions deeper than the excavations.

公开(公告)号：DE60037248T2

公开(公告)日：2008-10-09

申请号：DE60037248

申请日：2000-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA ,  ATTI MASSIMO ,  PALUMBO ELISABETTA ,  TORELLI COSIMO

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

Abstract: A lateral DMOS transistor having a drain region (13, 14) which comprises a high-concentration portion (14) with which the drain electrode (D) is in contact and a low-concentration portion (13) which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode (25) in contact with a point of the low-concentration portion of the drain region (13, 14) which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

公开(公告)号：IT1309102B1

公开(公告)日：2002-01-16

申请号：ITTO990884

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA

IPC: G11C16/04

Abstract: A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.

公开(公告)号：ITTO980516A1

公开(公告)日：1999-12-13

申请号：ITTO980516

申请日：1998-06-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZATELLI NICOLA ,  CREMONESI CARLO ,  CLEMENTI CESARE ,  PIO FEDERICO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.