公开(公告)号：DE69831921D1

公开(公告)日：2006-03-02

申请号：DE69831921

申请日：1998-12-04

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  SOURGEN LAURENT ,  ZATELLI NICOLA ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L23/556 ,  H01L23/58 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH07254293A

公开(公告)日：1995-10-03

申请号：JP28634994

申请日：1994-11-21

Applicant: ST MICROELECTRONICS SRL

Inventor： BALDI LIVIO ,  PIO FEDERICO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a method, with which a negative programming voltage is supplied to a non-volatile memory cell, suitable for integrated execution. CONSTITUTION: In order to supply the negative programming voltage to the non-volatile memory cell inside a non-volatile memory device, a 1st pole plate A of a capacitor C is connected through 1st switching means TX and TY to a positive high voltage source Vpp. Besides, a 2nd pole plate B of this capacitor C operationally connected to the control gate of one memory cell at least is connected through a 2nd switching means TB to a reference voltage source GND so that this capacitor can be charged at a positive high voltage. Next, the 1st pole plate of this capacitor is connected through the 1st switching means to the reference voltage source and the 2nd pole plate of this capacitor is disconnected from the reference voltage source so that a negative voltage can be provided on the 2nd pole plate.

公开(公告)号：JPH11265588A

公开(公告)日：1999-09-28

申请号：JP36090498

申请日：1998-12-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  ZATELLI NICOLA ,  SOURGEN LAURENT ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable the protection of an EEPROM cell which is improved with respect to abnormal readouts by allowing the cell to include floating-gate transistors, a first metallic layer over-lapping with a semiconductor substrate and a second metallic layer positioned by being more separated from the substrate than the first metallic layer and allowing the metallic first layer to be arranged so as to be overlapped in major portions of floating gate terminals. SOLUTION: A metallic structure for a screen 50 is arrayed so as to be overlapped on floating gate terminals 30 and covers only the terminals 30 completely. Since it is advantageous that the metallic structure 50 is formed in a first metallic layer, a selection terminal is provided by a poly silicon structure contacting in the relation that it is oven lapped with a metallic structure 242 formed in the first metallic layer in order to lower the low efficiency of a word line. Moreover, it is advantageous in order to obtain a small-sized cell layout that one side of readout terminals 14, 16 or both terminals are provided by a metallic structure to be formed in a metallic layer succeeding to the first metallic layer, that is, the second metallic layer.

公开(公告)号：JP2718902B2

公开(公告)日：1998-02-25

申请号：JP28634994

申请日：1994-11-21

Applicant: ST MICROELECTRONICS SRL

Inventor： BALDI LIVIO ,  PIO FEDERICO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH1174490A

公开(公告)日：1999-03-16

申请号：JP17749698

申请日：1998-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO ,  PIO FEDERICO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a simple manufacturing method of a semiconductor memory device having storage memory cells and shielded memory cells shielded so as to prevent their stored informations from being read out by external systems. SOLUTION: In the same chip made of semiconductor materials, there are formed at least one first memory cells each of which has a MOS transistor with overlapping first and second gates with each other formed respectively in first and second conductive material layers 12, 17 and at least one second memory cells each of which is so shielded by a shield material layer 32 that no external system can access to its storing information. This second memory cell comprises a MOS transistor having a floating gate formed of the first conductive material layer 12 simultaneously with the foregoing first gate electrode of the foregoing first memory cell, and the shield material layer 32 is formed of the second conductive material layer 17.

公开(公告)号：JPH0745730A

公开(公告)日：1995-02-14

申请号：JP2281894

申请日：1994-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To increase the reliability and life of a storage circuit, while reducing the deterioration of a tunnel oxide. CONSTITUTION: A double-level polysilicon EEPROM memory cell with a control gate 15 that is connected in series with a selective transistor 14 and is located at the upper layer of a floating gate 12 and a dielectric layer 11 between the gates has a region 10, consisting of an n -type region 18 and an n -type region.

公开(公告)号：JP2000208721A

公开(公告)日：2000-07-28

申请号：JP2000006540

申请日：2000-01-14

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  PAOLA ZULIANI ,  LORENZO FURATIN

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/00 ,  H01L23/58

Abstract: PROBLEM TO BE SOLVED: To prevent a COB(chip outline band) structure body from acting as an obstacle element, when the COB structure body is operated in an electromagnetic field. SOLUTION: This chip outline band (COB) structure body is used in a integrated circuit, which is integrated in a semiconductor chip having a first conductivity-type semiconductor substrate 1, and the substrate is biased to a common reference potential (GND) of the integrated circuit. The chip outline band structure body is provided with a substantially annular region 3 formed in the substrate 1 along its periphery, and at least annular conducting regions 40, 60 which is superposed on the annular region 3 and is in contact with the annular region 3. The region 3 is electrically connected with a point of the common reference potential (GND).

公开(公告)号：JPH11251452A

公开(公告)日：1999-09-17

申请号：JP37123998

申请日：1998-12-25

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  PIZZUTO OLIVIER

IPC: H01L21/28 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115

Abstract: PROBLEM TO BE SOLVED: To reduce the contact resistance and improve response speed by providing a high voltage transistor with a lightly doped drain region, and by providing a low voltage transistor with the lightly doped region and a more doped region adjacent to a gate region in the drain region and source region, respectively. SOLUTION: A drain region 6 of a high voltage transistor 2 is formed by implanting an N impurity to a substrate 1, and a source region 7 is formed by implanting an N impurity to the substrate 1. In the drain region 8 and the source region 9 of a low voltage transistor 3, a first part 10 is formed by implanting the N impurity to the substrate 1, and a second part 11 is formed by implanting the N impurity to the substrate 1, so as not to have the second part 11 aligned with a gate region 5. The gate region 5 is composed of a polysilicon layer insulated from the substrate 1 by another oxide layer, and a silicon oxide layer 23 that also covers the second part 11 is formed thereon. Then, in the drain region 6 and the source region 7 of the high voltage transistor, a contact region 4' which is doped higher with the impurity than the drain region 6, and the source region 7 is provided.

公开(公告)号：DE69941829D1

公开(公告)日：2010-01-28

申请号：DE69941829

申请日：1999-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： GOMIERO ENRICO ,  PIO FEDERICO ,  ZULIANI PAOLA

IPC: G11C16/04 ,  G11C16/12 ,  G11C16/30

Abstract: A non-volatile memory portion (1) includes a matrix of memory cells (2) comprising rows as the wordlines (WL) and columns as the bit-lines (BL). Control circuitry (3) includes a program voltage generator (7), an adjuster (25) of the voltage (Vst) applied to the matrix rows, a first adjuster (4) of an erase voltage (VppE) and a second adjuster (5) of a write voltage (VppW). The program voltage during the erasing phase is set higher than during the writing phase. An independent claim is also included for a process of fabricating a semiconductor non-volatile memory including forming a bit-switch element inside a well and a byte switch element directly in the substrate.

公开(公告)号：DE69739250D1

公开(公告)日：2009-03-26

申请号：DE69739250

申请日：1997-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/105 ,  H01L29/417 ,  H01L29/45

Abstract: An HV transistor (2) integrated in a semiconductor substrate (1) with a first type of conductivity, comprising a gate region (12) included between corresponding drain (16) and source (17) regions, and being of the type wherein at least said drain region (16) is lightly doped with a second type of conductivity. The drain region (16) comprises a contact region (7) with the second type of conductivity but being more heavily doped, from which a contact pad (21) stands proud.