公开(公告)号：JPH1168530A

公开(公告)日：1999-03-09

申请号：JP17706298

申请日：1998-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： GENOVA ANGELO ,  TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GARIBOLDI ROBERTO

IPC: H03K17/06

Abstract: PROBLEM TO BE SOLVED: To provide a circuit, capable of more efficiently charging a capacitance without increasing the power consumption for a parasitic transistor. SOLUTION: A circuit that charges a capacitance C with an LDMOS-LD integrated transistor is provided with a switching means SWb controlled by a logical signal UVLO. Hereby, the switching means SWb is made into active state, in order to charge a board node with the current whose maximum value is restricted to the pre-established value during a phase, in which a supply voltage Vs of an integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit.

公开(公告)号：JPH1174769A

公开(公告)日：1999-03-16

申请号：JP17734198

申请日：1998-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GENOVA ANGELO ,  GARIBOLDI ROBERTO

IPC: H03K17/06 ,  H03K17/08

Abstract: PROBLEM TO BE SOLVED: To automatically switch off an LDMOS transistor by having a zener diode which is biased forward between a supply node and a source node of an LDMOS transistor and providing a 2nd zener diode in place of a charging diode. SOLUTION: A 1st Zener diode Z1 is used in place of a charging diode of a capacity Cp which exists at Vs supply voltage. A 2nd Zener diode Z2 is connected between a source node S of a transistor LD and the supply node Vs. When Zehner voltages VZ1 and VZ2 of the diodes Z1 and Z2 satisfy the condition Vs>VZ1, there holds VTH>VZ1-VZ2, and when Vs Vs+ Vbe-VZ2 holds. VTH is the threshold voltage of the transistor LD, and the difference between the source voltage of the transistor LD and the substrate voltage is equal to VZ2-nVbe.

公开(公告)号：JPH11168369A

公开(公告)日：1999-06-22

申请号：JP19477998

申请日：1998-07-09

Applicant: ST MICROELECTRONICS SRL

Inventor： GENOVA ANGELO ,  CANTONE GIUSEPPE ,  GARIBOLDI ROBERTO

IPC: H03K5/08 ,  G05F3/26 ,  H03K17/16

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive integrated device of relatively simple and compact constitution without receiving interference at the time of switching. SOLUTION: In this integrated device 105 for a switching system provided with a control means 110 for generating switching control signals, a reference means 120 for generating a reference amount Qref and a means 110 for using the reference amount, the means 130 for storing the reference amount, a switch means 122 for connecting the reference means 120 to a using means 110 and a storage means 130 so as to supply the reference amount Qref in a first operation state and interrupting the reference means 120 from the using means 110, connecting the storage means 130 to the using means 110 and supplying the stored reference amount Qref in a second operation state and a filter means 135 for maintaining the switch means 122 in the second operation sate during a filtering period corresponding to the switching of control signals Sh are provided.

公开(公告)号：JPH1168531A

公开(公告)日：1999-03-09

申请号：JP17718598

申请日：1998-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GENOVA ANGELO ,  GARIBOLDI ROBERTO

IPC: H03K17/06 ,  H03K17/0812 ,  H03K17/16

Abstract: PROBLEM TO BE SOLVED: To surely control a gate voltage so that an LDMOS transistor can not be switched on undesiredly by providing a 2nd inverter provided with an input end, to which a 2nd logical signal is inputted and an output end which is connected to a gate node of the LDMOS transistor. SOLUTION: In a pMOS transistor M1, its source is connected to the cathode of a diode D1 and to a charging terminal of a bootstrap capacitor Cp, also its drain is connected to the drain of an nMOS transistor M2 and to the gate of an LDMOS integrated transistor LD. The source of the transistor M2 is connected to an output node A of a control inverter 101 and to the other terminal of the condenser Cp. Then gates of the transistors M1 and M2 are controlled by a logical signal UVLOb and prevent the transistor LD from being turned on accidentally.

公开(公告)号：ITVA20000031D0

公开(公告)日：2000-09-07

申请号：ITVA20000031

申请日：2000-09-07

Applicant: ST MICROELECTRONICS SRL

Inventor： GENOVA ANGELO ,  GARIBOLDI ROBERTO ,  NOVELLI ALDO ,  RICOTTI GIULIO

IPC: G01R19/165

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

公开(公告)号：DE69727807D1

公开(公告)日：2004-04-01

申请号：DE69727807

申请日：1997-10-10

Applicant: ST MICROELECTRONICS SRL

Inventor： GENOVA ANGELO ,  GARIBOLDI ROBERTO ,  CANTONE GIUSEPPE

IPC: H03K3/011 ,  H03K3/0232 ,  H03K3/355

公开(公告)号：DE69725126D1

公开(公告)日：2003-10-30

申请号：DE69725126

申请日：1997-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PAPPALARDO SALVATORE ,  NOVELLI ALDO ,  GENOVA ANGELO ,  DE MARCO ALBERTO

IPC: H02M1/00 ,  H02M1/38 ,  H02P8/14 ,  H02M7/538

Abstract: In multiphase driving systems of electric motors in a switching mode employing distinct integrated half-bridge output stages, the use of multiple external components for each integrated half-bridge stage to implement functions of adjustment of the switching dead-time and of disabling/enabling of the half-bridge stage can be avoided and an improved matching obtained by using single external components connected in common to the dedicated pins of all the distinct integrated half-bridge output stages. This is achieved by duplicating the disabling comparator, respectfully for the power transistor of the pull-up branch and for the power transistor of the pull-down branch in each integrated half-bridge stage.

公开(公告)号：IT1313850B1

公开(公告)日：2002-09-24

申请号：ITMI992469

申请日：1999-11-25

Applicant: ST MICROELECTRONICS SRL

Inventor： NOVELLI ALDO ,  GARIBOLDI ROBERTO ,  GENOVA ANGELO ,  FILIPPO ROBERTO

IPC: H03K17/0412 ,  H03K17/06

Abstract: A high side circuit is described which comprises at least one power device (1) having a first non drivable terminal (D) connected to a supply voltage (Vcc), at least one load (2) connected between a second non drivable terminal (S) of the power device (1) and ground, and driving circuitry (10). The driving circuitry (10) comprises suitable dimensioned transistors (M1, M2, M3) which are connected to each other and to a higher voltage (Vboot) than the supply voltage (Vcc) in order to control the turning on and the turning off of the power device (1) and to minimize the potential difference between the second non drivable terminal (S) and a drivable terminal (G) of the power device (1) during the turning off state to avoid the re-turning on of the same power device.

公开(公告)号：DE69705217T2

公开(公告)日：2001-09-20

申请号：DE69705217

申请日：1997-08-07

Applicant: ST MICROELECTRONICS SRL

Inventor： GENOVA ANGELO ,  CANTONE GIUSEPPE ,  GARIBOLDI ROBERTO

IPC: H03K5/08 ,  G05F3/26 ,  H03K17/16 ,  G05F1/00 ,  G05F1/575

公开(公告)号：ITMI992469A1

公开(公告)日：2001-05-25

申请号：ITMI992469

申请日：1999-11-25

Applicant: ST MICROELECTRONICS SRL

Inventor： NOVELLI ALDO ,  GARIBOLDI ROBERTO ,  GENOVA ANGELO ,  FILIPPO ROBERTO

IPC: H03K17/0412 ,  H03K17/06

Abstract: A high side circuit is described which comprises at least one power device (1) having a first non drivable terminal (D) connected to a supply voltage (Vcc), at least one load (2) connected between a second non drivable terminal (S) of the power device (1) and ground, and driving circuitry (10). The driving circuitry (10) comprises suitable dimensioned transistors (M1, M2, M3) which are connected to each other and to a higher voltage (Vboot) than the supply voltage (Vcc) in order to control the turning on and the turning off of the power device (1) and to minimize the potential difference between the second non drivable terminal (S) and a drivable terminal (G) of the power device (1) during the turning off state to avoid the re-turning on of the same power device.