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    3.
    发明专利
    未知

    公开(公告)号：ITMI981376A1

    公开(公告)日：1999-12-16

    申请号：ITMI981376

    申请日：1998-06-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PINTO ANGELO ,  PALARA SERGIO

    IPC: H01L21/265 ,  H01L21/331

    Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

    4.
    发明专利
    未知

    公开(公告)号：IT1301729B1

    公开(公告)日：2000-07-07

    申请号：ITMI981376

    申请日：1998-06-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PINTO ANGELO ,  PALARA SERGIO

    IPC: H01L21/265 ,  H01L21/331

    Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

    5.
    发明专利
    未知

    公开(公告)号：DE69714575D1

    公开(公告)日：2002-09-12

    申请号：DE69714575

    申请日：1997-05-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PINTO ANGELO ,  ALEMANNI CARLO

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732 ,  H01L29/735

    Abstract: The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure and comprising: the semiconductor substrate, doped with impurities of the P type; a first buried layer, doped with impurities of the N type to form a base region; a second layer (13), overlying the first and having conductivity of the N type, to form an active area; opposite collector (12) and emitter (14) regions being formed in said active area and separated by a base channel region; characterized in that the width of the base channel is defined essentially by a contact opening (18) formed above an oxide layer (11) protecting the base channel. Advantageously, the opening (18) is formed by shifting an emitter mask.

    6.
    发明专利
    未知

    公开(公告)号：DE69806484D1

    公开(公告)日：2002-08-14

    申请号：DE69806484

    申请日：1998-11-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATTI DAVIDE ,  PINTO ANGELO

    IPC: H01L21/336 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8249 ,  H01L29/78

    Abstract: The following steps are performed on a wafer of semiconductor material having a layer (1) with n conductivity: a) implanting n impurity ions and p impurity ions in an area of the layer and subjecting the wafer to a high-temperature treatment; the impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first, p region (49) and a second, n region (50) which forms a pn junction with the first region (49); b) hollowing out a trench (43) which intersects the first region (49) and the second region (50), c) forming a dielectric coating (44) on the lateral surface of the trench (43), d) depositing electrically-conductive material (51) in the trench (43) in contact with the dielectric (44), and e) forming elements (60, 61, 62) for electrical contact with the layer (1), with the second region (50), and with the electrically-conductive material (51) inside the trench (43), in order to produce drain (D), source (S) and gate (G) electrodes of the MOSFET, respectively. A submicrometric vertical-channel MOSFET of optimal quality and reproducibility is thus produced by a method compatible with DPSA technology.

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