公开(公告)号：DE69921086D1

公开(公告)日：2004-11-18

申请号：DE69921086

申请日：1999-02-26

Applicant: ST MICROELECTRONICS SRL ,  WAFERSCALE INTEGRATION INC

Inventor： POZZONI PIERANTONIO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO ,  IRANI RUSTON

IPC: H01L21/8247

公开(公告)号：JP2003163294A

公开(公告)日：2003-06-06

申请号：JP2002294069

申请日：2002-10-07

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPRARA PAOLO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To simplify the step of manufacturing a double charge storage location memory cell. SOLUTION: A dielectric stack 120 is disposed over the entire upper side surface of a structure. A contact opening 121 is formed in the dielectric layer 120 lowered to the surface of a bit line diffused part 115 of the specified region at the outside of the memory cell sub-array. Metal bit lines 123A, 123B are specified to cross a word line 119 on the bit line diffused part 115 so as to bring into contact with the position corresponding to the specified region by a normal contact forming technique and a metallization technique. The metal bit line restricts the voltage drop along the bit line diffused part 115. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001168303A

公开(公告)日：2001-06-22

申请号：JP24214498

申请日：1998-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

IPC: G11C16/04 ,  G11C8/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a new method of manufacturing an electronic memory device which is integrated on a semiconductor containing a virtual ground cell matrix. SOLUTION: A matrix is formed on a semiconductor substrate 10 as it is provided with continuous bit lines 7 which extend as discrete parallel stripes traversing a substrate 10. The matrix contains a circuit part C' for selective transistors 20, and a decoder equipped with a P-channel and an N-channel MOS transistor and an address circuits A and B are built in a memory device. A process in which an N well 11 where the P-channel transistor is housed is formed on a part A of the substrate, and another process in which the active regions of all transistors are specified by a screen mask 33 and an isolation layer 13 is grown through the intermediary of an opening provided to the mask 33, are at least provided. The active region specifying mask 33 is not opened on the matrix region C" of the memory cell.

公开(公告)号：DE69732838D1

公开(公告)日：2005-04-28

申请号：DE69732838

申请日：1997-07-16

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  GINAMI GIANCARLO

IPC: H01L21/8247 ,  H01L23/528 ,  H01L27/105 ,  H01L27/115

Abstract: A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD), said defining the second strips (17) providing for selectively etching the first and second layers of conductive material (9,11) outside the memory cell array area by means of a first mask (MASK1), and said defining the first strips (22) providing for selectively etching the second layer of conductive material (11), the layer of insulating material (10) and the first layer of conductive material (9) inside the memory cell array area by means of a second mask (MASK2). The first and second masks (MASK1,MASK2) overlap in a boundary region around the memory cell array area, so that the first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

公开(公告)号：DE69732293D1

公开(公告)日：2005-02-24

申请号：DE69732293

申请日：1997-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CASSIO VALERIO ,  BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

公开(公告)号：DE69631029D1

公开(公告)日：2004-01-22

申请号：DE69631029

申请日：1996-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  GINAMI GIANCARLO ,  DAFFRA STEFANO ,  RAVAGLIA ANDREA ,  CEREDA MANLIO SERGIO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, which comprises the following steps: -- forming field oxide regions (14) and drain active area regions (15) on a substrate (1); -- forming word lines (16) on the field oxide regions (14); -- depositing oxide to form oxide wings (13) that are adjacent to the word lines (16); characterized in that it comprises the following additional steps: -- opening, by masking (20), source regions (18) and the drain active area regions (15), keeping the field oxide regions (14) that separate one memory cell from the other, inside the memory, covered with resist; and -- removing field oxide (14) in the source regions (18) and removing oxide wings (13) from both sides of the word lines (16).

公开(公告)号：DE69739045D1

公开(公告)日：2008-11-27

申请号：DE69739045

申请日：1997-08-27

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CASSIO VALERIO ,  CAPRARA PAOLO ,  CEREDA MANLIO SERGIO

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

Abstract: The invention relates to a process for manufacturing electronic virtual ground memory devices integrated on a semiconductor and including a matrix (3) of floating gate memory cells, the matrix being formed on a semiconductor substrate (10) with a plurality of continuous bit lines (7) extending across the substrate (10) as discrete parallel stripes. The matrix includes a circuit portion (C') for selection transistors (20), and the memory devices incorporating decode and address circuit portions (A,B) having P-channel and N-channel MOS transistors. The inventive process comprises at least the following steps: forming N-wells (11) in at least one (A) of said substrate portions to accommodate said P-channel transistors, defining the active areas of all the transistors by means of a screening mask (33), and then growing an isolation layer (13) through the apertures of said mask (33). The active area definition mask (33) is not open over the matrix region (C'') of the memory cells.

公开(公告)号：DE69926733D1

公开(公告)日：2005-09-22

申请号：DE69926733

申请日：1999-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA CLAUDIO ,  CEREDA MANLIO SERGIO ,  CAPRARA PAOLO

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522

Abstract: An improved method for autoaligning lines (WL) of a conductive material in circuits integrated on a semiconductor substrate (2), comprising the following steps: forming, on said semiconductor substrate (2), a plurality of regions (3) projecting from the substrate (2) surface and aligned to one another; forming a fill layer (4) in the gaps between said regions (3) ; planarizing said fill layer (4) to expose said regions (3) ; removing a surface portion of said regions (3) to form holes (5) at the locations of said regions (3); forming an insulating layer (6) in said holes (5); selectively removing the dielectric layer (6) to form spacers (7) along the edges of said holes (5) ; depositing at least one conductive layer (8) all over the exposed surface; photolithographing with a mask and etching away the layer (8) to define lines (WL) and collimate them to the underlying regions (3).