公开(公告)号：WO2004112128A3

公开(公告)日：2005-07-14

申请号：PCT/US2004016347

申请日：2004-05-25

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  ROPER DAVID ,  BUCHLE JEFF

Inventor： CADY JAMES ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  ROPER DAVID ,  BUCHLE JEFF

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing such mounted devices for stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Abstract translation: 本发明提供一种将集成电路器件安装到衬底上的系统和方法，以及用于使用这种安装的器件用于堆叠模块的系统和方法。 封装的集成电路器件的接触焊盘基本上露出。 将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。 集成电路器件定位成与衬底的触点接触。 施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。 形成的接头在随后的加工步骤中较少受到再熔化。 该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中所公开的那些。 通常，创建的关节的轮廓较低。

公开(公告)号：WO2005098941A3

公开(公告)日：2006-07-13

申请号：PCT/US2005010756

申请日：2005-03-30

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  WILDER JAMES ,  ROPER DAVID ,  WEHRLY JR DOUGLAS

Inventor： CADY JAMES ,  WILDER JAMES ,  ROPER DAVID ,  WEHRLY JR DOUGLAS

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/31 ,  H01L23/34 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules 10 provided herewith. In a preferred embodiment in accordance with the invention, a form standard 34 provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design 32. In a preferred embodiment, the form standard 34 will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard 34 may include a heat spreader portion 192 with mounting feet 198. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module 10 to reduce the loading effect upon data signals in memory access.

Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块10。 在根据本发明的优选实施例中，形式标准34提供允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计32时被有利地使用的物理形式。 优选实施例中，将设计出诸如铜之类的热转移材料的形式标准34以改善热性能。 在替代实施例中，形式标准34可以包括具有安装脚198的散热器部分19.在存储器寻址系统的优选实施例中，高速切换系统选择与堆叠模块10的每个级别相关联的数据线 减少存储器访问中数据信号的负载效应。

公开(公告)号：WO2005114726A2

公开(公告)日：2005-12-01

申请号：PCT/US2005016764

申请日：2005-05-11

Applicant: STAKTEK GROUP LP ,  WEHRLY DOUGLAS JR ,  CADY JAMES ,  PARTRIDGE JULIAN ,  ROPER DAVID

Inventor： WEHRLY DOUGLAS JR ,  CADY JAMES ,  PARTRIDGE JULIAN ,  ROPER DAVID

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/02

CPC classification number: H01L25/105 ,  H01L23/3114 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/107

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or more conductive layers with preferred embodiments having two conductive layers. A form standard is disposed along the lower planar surface and extends laterally beyond the package of one or more CSPs in a stacked module. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be comprised of heat conductive material such as copper, for example.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 该柔性电路可以呈现一个或多个导电层，优选实施例具有两个导电层。 形式标准沿着下平面表面设置并横向延伸超过堆叠模块中的一个或多个CSP的包装。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在优选实施例中，形式标准例如由导热材料例如铜构成。

公开(公告)号：WO2005010990A3

公开(公告)日：2005-05-06

申请号：PCT/US2004023152

申请日：2004-07-20

Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  RAPPORT RUSSELL ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  WILDER JAMES ,  ROPER DAVID ,  BUCHLE JEFF

Inventor： CADY JAMES ,  RAPPORT RUSSELL ,  PARTRIDGE JULIAN ,  WEHRLY JAMES JR ,  WILDER JAMES ,  ROPER DAVID ,  BUCHLE JEFF

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/373 ,  H01L23/485

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM. Although the present invention is preferably employed to advantage using stacked modules comprised from multiple CSPs, it may be employed with modules comprised from any number and type of integrated circuits including any type of packaging, whether CSP or leaded. The stacked modules make use of flexible substrates, low-profile contacts and form standarads for folding substrates.

Abstract translation: 通过使用堆叠模块，提供了用于多个集成存储器电路的点对点寻址的系统和方法。 单个存储器扩展板上装有集成电路的堆叠模块。 在优选实施例中，不使用堆叠的四个DIMM插槽存储器存取总线被单个DIMM插槽总线替代，该DIMM插槽总线在单个DIMM上支持堆叠高达四个高。 虽然本发明优选地使用由多个CSP组成的堆叠模块，但是可以使用包括任何数量和类型的集成电路的模块，包括任何类型的封装，无论是CSP还是带引线。 堆叠的模块使用柔性基板，低轮廓接触和形成用于折叠基板的标准。

公开(公告)号：EP1730774A4

公开(公告)日：2009-11-25

申请号：EP05735041

申请日：2005-03-30

Applicant: STAKTEK GROUP LP

Inventor： CADY JAMES ,  WILDER JAMES ,  ROPER DAVID ,  WEHRLY JR DOUGLAS

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/31 ,  H01L23/34 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401