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    Chip scale stacking system and method
    1.
    发明专利
    Chip scale stacking system and method 未知

    公开(公告)号：GB2395367A

    公开(公告)日：2004-05-19

    申请号：GB0406140

    申请日：2002-10-25

    Applicant: STAKTEK GROUP LP

    Inventor： CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L ,  WEHRLY JAMES DOUGLAS ,  DOWDEN JULIAN ,  BUCHLE JEFF

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48 ,  H05K1/00

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module (10) devised in accordance with a preferred embodiment of the present invention, a pair of CSPs (12, 14) is stacked, with one CSP (12) above the other (14). The two CSPs are connected with a pair of flexible circuit structures (30, 32). Each of the pair of flexible circuit structures (30, 32) is partially wrapped about a respective opposite lateral edge (20, 22) of the lower CSP (14) of the module (10). The flex circuit pair (30, 32) connects the upper and lower CSPs (12, 14) and provides a thermal and electrical path connection path between the module (10) and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.

    Chip scale stacking system and method
    2.
    发明专利
    Chip scale stacking system and method 未知

    公开(公告)号：GB2395367B

    公开(公告)日：2005-05-25

    申请号：GB0406140

    申请日：2002-10-25

    Applicant: STAKTEK GROUP LP

    Inventor： CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L ,  WEHRLY JAMES DOUGLAS ,  DOWDEN JULIAN ,  BUCHLE JEFF

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48 ,  H05K1/00

    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

    MEMORY EXPANSION AND INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD
    3.
    发明专利
    MEMORY EXPANSION AND INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD 未知

    公开(公告)号：AU2003304192A1

    公开(公告)日：2005-01-04

    申请号：AU2003304192

    申请日：2003-09-15

    Applicant: STAKTEK GROUP LP

    Inventor： WEHRLY JAMES DOUGLAS JR ,  BUCHLE JEFF ,  RAPPORT RUSSELL ,  CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L

    IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

    A HIGH-DENSITY CIRCUIT MODULE
    4.
    发明专利
    A HIGH-DENSITY CIRCUIT MODULE 未知

    公开(公告)号：HK1077460A1

    公开(公告)日：2006-02-10

    申请号：HK05109243

    申请日：2005-10-22

    Applicant: STAKTEK GROUP LP

    Inventor： CADY JAMES W ,  WILDER JAMES ,  ROPER DAVID L ,  WEHRLY JAMES DOUGLAS ,  DOWDEN JULIAN ,  BUCHLE JEFF

    IPC: H01L20090101 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

    THIN CIRCUIT MODULE AND METHOD
    7.
    发明申请
    THIN CIRCUIT MODULE AND METHOD 审中-公开
    薄膜电路模块和方法

    公开(公告)号：WO2009039263A3

    公开(公告)日：2009-10-15

    申请号：PCT/US2008076839

    申请日：2008-09-18

    Applicant: STAKTEK GROUP LP ,  WOLFE MARK ,  WILDER JAMES ,  ROPER DAVID L

    Inventor： WOLFE MARK ,  WILDER JAMES ,  ROPER DAVID L

    IPC: H01R12/16 ,  G06F12/00 ,  H01R13/10 ,  H01R13/62

    CPC classification number: H05K1/183 ,  H05K1/0203 ,  H05K1/117 ,  H05K2201/09972 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  Y10T29/49124

    Abstract: A circuit module includes a printed circuit board (PCB) (12) having a first side (22), a second side (24), and a bottom perimeter edge (42). The PCB exhibits a first thickness along the bottom perimeter edge. The first side includes a recessed area (70) and, in that recessed area, the PCB has a second thickness that is less than the first thickness. A plurality of integrated circuits (ICs) are fixed to the PCB in the recessed area. A plurality of module contacts (30) are connected to the ICs and are disposed along at least one of the first and second sides and are configured to provide electrical connection between the circuit module and an edge connector.

    Abstract translation: 电路模块包括具有第一侧面（22），第二侧面（24）和底部周边边缘（42）的印刷电路板（PCB）（12）。 PCB沿底部周边边缘呈现第一厚度。 第一侧包括凹入区域（70），并且在该凹入区域中，PCB具有小于第一厚度的第二厚度。 多个集成电路（IC）被固定到凹陷区域中的PCB。 多个模块触点（30）连接到IC并且沿着第一和第二侧中的至少一个设置，并且被配置为提供电路模块和边缘连接器之间的电连接。

    STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD
    9.
    发明申请
    STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD 审中-公开
    堆叠集成电路CASCADE信号系统和方法

    公开(公告)号：WO2006028693A3

    公开(公告)日：2009-09-03

    申请号：PCT/US2005029867

    申请日：2005-08-23

    Applicant: STAKTEK GROUP LP ,  CADY JAMES ,  RAPPORT RUSSELL ,  WILDER JAMES

    Inventor： CADY JAMES ,  RAPPORT RUSSELL ,  WILDER JAMES

    IPC: H01L23/02 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L23/04 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L25/105 ,  H01L23/4985 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Integrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded series of conductive paths. In another preferred embodiment, a form standard provides a physical form that allows many of the varying package sizes found in a broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

    Abstract translation: 集成电路（IC）堆叠成可以节省PCB或其他板表面积的模块。 这些模块提供了较低电容存储器信号系统和用于以串联级联布置连接堆叠CSP的方法。 在一个优选实施例中，选择性地使用管芯端子来终止级联的导电路径。 在另一个优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在宽范围的CSP封装系列中发现许多变化的封装尺寸。

    CIRCUIT MODULE WITH THERMAL CASING SYSTEMS AND METHODS
    10.
    发明申请
    CIRCUIT MODULE WITH THERMAL CASING SYSTEMS AND METHODS 审中-公开
    具有热壳系统和方法的电路模块

    公开(公告)号：WO2006121487A3

    公开(公告)日：2007-11-22

    申请号：PCT/US2006007004

    申请日：2006-02-28

    Applicant: STAKTEK GROUP LP ,  WEHRLY JAMES DOUGLAS JR ,  WILDER JAMES ,  WOLFE MARK ,  GOODWIN PAUL

    Inventor： WEHRLY JAMES DOUGLAS JR ,  WILDER JAMES ,  WOLFE MARK ,  GOODWIN PAUL

    IPC: H01L23/34

    CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

    Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. The populated flexible circuitry is disposed about an edge of a rigid substrate preferably devised from thermally-conductive materials and one or more thermal spreaders are disposed in thermal contact with at least some of the constituent integrated circuitry of the module. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.

    Abstract translation: 灵活的电路装有沿主要侧面或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 填充的柔性电路围绕刚性衬底的边缘设置，优选地由导热材料设计，并且一个或多个散热器布置成与模块的组成集成电路中的至少一些热接触。 可选地，作为附加的热管理特征，模块可以包括设置在较高热能IC器件附近的高导热性散热器或区域。 在优选实施例中，来自衬底主体或衬底芯的延伸部促进模块的IC之间的热变化减小，同时提供用于从模块中排出热能的放大表面。

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