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    Memory cell integrated structure and corresponding biasing device
    1.
    发明公开
    Memory cell integrated structure and corresponding biasing device 失效
    Vorspannungsvorrichtungfürintegrierte Speicherzellenstruktur

    公开(公告)号：EP0952615A1

    公开(公告)日：1999-10-27

    申请号：EP98830238.6

    申请日：1998-04-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Zanardi, Stefano ,  Branchetti, Maurizio ,  Ghezzi, Stefano

    IPC: H01L27/115 ,  G05F3/20

    CPC classification number: H01L27/115 ,  G05F3/205

    Abstract: The invention relates to an integrated structure (1) for memory cells formed over a semiconductor substrate (2) doped with a first dopant type and including at least one memory cell (CM) in turn formed in a conductive well (3) provided in said semiconductor substrate (2) and doped with a second dopant type, said conductive well (3) having an additional well (4) formed therein which is doped with the first dopant type and comprises active areas (5,6) of the memory cell (CM).
    According to the invention, a substrate bias terminal (8), formed in the additional well (4), is further associated with the memory cell (CM) to receive a suitable bias voltage (Vpol) to lower the threshold voltage (Vth) of the memory cell (CM) by body effect.
    The invention also relates to a biasing device (13) for a memory cell (CM) which has at least one substrate bias terminal (8) associated therewith, the biasing device comprising at least a first sub-threshold circuitry block (A) adapted to supply an appropriate current during the device standby phase through a restore transistor (M1) connected between a supply voltage reference (Vcc) and the substrate bias terminal (8) of the memory cell (CM), and having a control terminal connected to a bias circuit (14), in turn connected between the supply voltage reference (Vcc) and a ground voltage reference (GND) to drive the restore transistor (M1) with a current of limited value.
    The device according to the invention further comprises a second feedback block (B) for fast charging the substrate bias terminal (8), being connected between the supply voltage reference (Vcc) and the ground voltage reference (GND) and comprising a first bias transistor (M2) having a control terminal connected to the ground voltage reference (GND) via a stabilization transistor (M3), having in turn a control terminal connected to an output node (OC), and to the control terminal of a first regulation transistor (M4) connected between the supply voltage reference (Vcc) and the ground voltage reference (GND), the stabilization transistor (M3) and first regulation transistor (M4) providing feedback for the bias transistor (M2), thereby to restrict the voltage range of the output node (OC).

    Abstract translation: 本发明涉及一种用于存储单元的集成结构（1），其形成于掺杂有第一掺杂剂类型的半导体衬底（2）上，并且还包括至少一个存储单元（CM），所述至少一个存储单元又形成在所述导电阱 半导体衬底（2）并掺杂有第二掺杂剂类型，所述导电阱（3）具有形成在其中的附加阱（4），其中掺杂有第一掺杂剂类型，并且包括存储器单元的有源区（5,6） 厘米）。 根据本发明，形成在附加阱（4）中的衬底偏置端子（8）还与存储单元（CM）相关联以接收合适的偏置电压（Vpol）以降低阈值电压（Vth） 记忆体（CM）通过身体效应。 本发明还涉及一种用于存储单元（CM）的偏置装置（13），其具有至少一个与其相关联的衬底偏置端子（8），所述偏置装置至少包括第一子阈值电路块（A） 在器件待机阶段通过连接在电源电压基准（Vcc）和存储单元（CM）的衬底偏置端子（8）之间的还原晶体管（M1）提供适当的电流，并且具有连接到偏置的控制端子 电路（14）又连接在电源电压基准（Vcc）和接地电压基准（GND）之间，以限制电流驱动恢复晶体管（M1）。 根据本发明的装置还包括用于对衬底偏置端子（8）进行快速充电的第二反馈块（B），其连接在电源电压参考（Vcc）和接地电压基准（GND）之间，并且包括第一偏置晶体管 （M2），其具有经由稳定晶体管（M3）连接到接地电压基准（GND）的控制端子，其具有连接到输出节点（OC）的控制端子和第一调节晶体管（...的控制端子） M4）连接在电源电压基准（Vcc）和接地电压基准（GND）之间，稳定晶体管（M3）和第一调节晶体管（M4）为偏置晶体管（M2）提供反馈，从而限制 输出节点（OC）。

    Memory device having improved yield and reliability
    5.
    发明授权
    Memory device having improved yield and reliability 失效
    具有改进的可靠性和改进的结果存储装置

    公开(公告)号：EP0766174B1

    公开(公告)日：2002-05-22

    申请号：EP95830408.1

    申请日：1995-09-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Branchetti, Maurizio ,  Golla, Carla ,  Campardo, Giovanni

    IPC: G06F11/10

    CPC classification number: G06F11/1008

    Abstract: The present invention relates to a memory device of the type comprising: at least one first (M1) and one second (M2) memory cell array for storage respectively of a first plurality of user data and a second plurality of error identification and correction data, first (D1) and second (D2) decoding means connected respectively to the first (M1) and second (M2) memory cell array for selection and reading respectively of the first and second pluralities of data, error identification means (L1) coupled to said first (D1) and second (D2) decoder means, and error correction means (C1,C2,EN) operationally connected to said first (D1) and second (D2) decoder means and to said error identification means (L1), and characterized in that it comprises at least one logical control unit (L2) operationally connected to the second decoder means (D2), to error identification means (L1) and to the error correction means (C1,C2,EN) to enable said second decoder means (D2) and said error correction means (C1,C2,EN) if an error is detected by the error identification means (L1).

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