公开(公告)号：EP1408549B1

公开(公告)日：2007-03-07

申请号：EP02425604.2

申请日：2002-10-08

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Pellizzer, Fabio ,  Casagrande, Giulio ,  Gastaldi, Roberto ,  Vendrame, Loris ,  Benvenuti, Augusto ,  Lowrey, Tyler, c/o Ovonyx Inc.

IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

公开(公告)号：EP1408549A1

公开(公告)日：2004-04-14

申请号：EP02425604.2

申请日：2002-10-08

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Pellizzer, Fabio ,  Casagrande, Guilio ,  Gastaldi, Roberto ,  Vendrame, Loris ,  Benvenuti, Augusto ,  Lowrey, Tyler, c/o Ovonyx Inc.

IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

Abstract: A process for manufacturing an array of cells, including: implanting, in a body (10) of semiconductor material of a first conductivity type, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer (21) having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings (27a) with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions (14) of the first conductivity type; implanting second portions of the active area regions through the second openings (27b) with a doping agent of the second conductivity type, thereby forming control contact regions (15) of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components (3), each storage component having a terminal connected to a respective second conduction region (14).

Abstract translation: 单元的阵列是通过注入第一导电类型，以通过绝缘层的第一开口有源区区域的第一部分的掺杂剂，以形成第二导电区制成; 注入第二导电类型到穿过绝缘层以形成控制接触区域的第二开口的有源区域的区域的第二部分中的掺杂剂; 和在所述主体的顶部上形成存储元件。 单元阵列的制造包括：提供第一导电类型的半导体材料的本体（10）; 植入在身体中，第一导电类型的公共导电区（11）; 形成在所述主体中，公共导电区域上方，有源区的区域的第二导电类型和第一掺杂水平的（12）; 形成，在所述主体的顶部，绝缘层上具有第一和第二开口（27A，27B）; 通过用第一导电类型的掺杂剂的第一开口注入所述有源区区域的第一部分，从而形成在所述有源区区域中的第一导电类型的第二传导区域; 通过注入与所述第二导电类型的掺杂剂的第二孔中的活性区域的区域的第二部分，所述第二导电类型和第二掺杂水平比所述第一掺杂等级高的形成，从而控制接触区域（15）; 并形成存储元件（24）在所述主体的顶部上。 每个控制接触区域形成，与所述第二传导区域和公共传导区，选择双极型晶体管（20）连接在一起。 每个存储组件具有连接到第二respectivement传导区的端子。 它定义，与双极晶体管，所述单元阵列的细胞一起。

公开(公告)号：EP1376698A1

公开(公告)日：2004-01-02

申请号：EP02425416.1

申请日：2002-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Ghezzi, Paolo ,  Maurelli, Alfonso ,  Vendrame, Loris ,  Zabberoni, Paola

IPC: H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

Abstract: An electrically erasable and programmable non-volatile memory cell (205) integrated in a chip of semiconductor material (300) is proposed. The memory cell includes a floating gate MOS transistor (210m) having a source region (335) and a drain region (325) formed in a first well (315), a channel (340) being defined between the drain region and the source region during operation of the memory cell, a control gate region (350), and a floating gate (355) extending over the channel and the control gate region, and a bipolar transistor (215) for injecting an electric charge into the floating gate, the bipolar transistor having an emitter region (365) formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel, wherein the memory cell further includes a second well (320) insulated from the first well, the control gate region being formed in the second well.

Abstract translation: 提出了集成在半导体材料（300）的芯片中的电可擦除和可编程的非易失性存储单元（205）。 存储单元包括具有形成在第一阱（315）中的源极区（335）和漏极区（325）的浮置栅极MOS晶体管（210m），在漏极区域和源极区域之间限定沟道（340） 在所述存储单元的操作期间，在所述通道和所述控制栅极区域上延伸的控制栅极区域（350）和浮置栅极（355）以及用于将电荷注入所述浮动栅极的双极晶体管（215） 双极晶体管，其具有形成在第一阱中的发射极区域（365），由第一阱构成的基极区域和由沟道组成的集电极区域，其中存储单元还包括与第一阱绝缘的第二阱（320） ，所述控制栅极区域形成在所述第二阱中。

公开(公告)号：EP1220321A1

公开(公告)日：2002-07-03

申请号：EP00830851.2

申请日：2000-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Vendrame, Loris ,  Caprara, Paolo ,  Oddone, Giorgio ,  Barcella, Antonio

IPC: H01L29/732 ,  H01L29/08

CPC classification number: H01L29/7322 ,  H01L29/0813

Abstract: The present invention relates a transistor comprising a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of said first type (P+) of conductivity inside said substrate region (14) and adjacent to a first terminal (C) of said transistor, a well (11) of second type (N) of conductivity placed inside said substrate region (14), characterized in that said well (11) of second type (N) of conductivity comprises at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of said transistor, and a plurality of third contact regions (10) of said first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, ..., E3) of said transistor interposed each one (10) other (12) by proper insulating shapes (20).

Abstract translation: 本发明涉及一种晶体管，其包括在具有相同类型（P）导电性的半导体材料层中的第一类型（P）的基底区域（14），至少第一类型的第一接触区域（13） （14）内并与所述晶体管的第一端（C）相邻的电导率（P +），放置在所述衬底区域（14）内的第二类型（N）导电性阱（11），其特征在于： 所述第二类型（N）的导体的阱（11）包括与所述晶体管的第二端子（B）的区域相邻的至少第二接触区域（N）的第二接触区域（12），并且多个 与所述晶体管的第三端子（E1，...，E3）的多个区域相邻的所述第一类型导电性（P +）的第三接触区域（10）通过适当地插入每个（10）另一个（12） 绝缘形状（20）。

公开(公告)号：EP1475642B1

公开(公告)日：2006-07-19

申请号：EP03425282.5

申请日：2003-05-02

Applicant: STMicroelectronics S.r.l.

Inventor： Bortesi, Luca ,  Vendrame, Loris ,  Bogliolo, Alessandro

IPC: G01R27/26

CPC classification number: G01R27/2605 ,  G01R31/026 ,  G01R31/2853

公开(公告)号：EP1640994A1

公开(公告)日：2006-03-29

申请号：EP04104595.6

申请日：2004-09-22

Applicant: STMicroelectronics S.r.l.

Inventor： Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Benvenuti, Augusto ,  Vendrame, Loris ,  Zuliani, Paola

IPC: G11C16/02 ,  G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

Abstract: A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

Abstract translation: 提出了一种存储器件。 存储器件包括多个存储器单元（P，S），其中每个存储器单元包括用于在读取操作或编程操作期间选择相应的存储元件的存储元件（P）和选择器（S）。 选择器包括单极元件（M）和双极元件（D; B）。 存储器件还包括控制装置（110s），用于在编程操作期间在读取操作期间使单极元件能够被普遍使能或双极元件。

公开(公告)号：EP1475642A1

公开(公告)日：2004-11-10

申请号：EP03425282.5

申请日：2003-05-02

Applicant: STMicroelectronics S.r.l.

Inventor： Bortesi, Luca ,  Vendrame, Loris ,  Bogliolo, Alessandro

IPC: G01R27/26

CPC classification number: G01R27/2605 ,  G01R31/026 ,  G01R31/2853

Abstract: A method and a corresponding arrangement for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. The method and arrangement solve the problem of short-circuit currents that affects the known test structures, and allow a direct measurement of the coupling capacitance between the two interconnect lines.
Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.

Abstract translation: 一种用于测量两条互连线之间的耦合电容的方法和相应的装置利用了所谓的串扰效应，并在一定的基准电压互连线保持。 该方法和装置解决的短路电流的故障确实影响了已知的测试结构，并允许两条互连线之间的耦合电容的直接测量。 因此电容测量可以用于互连线中断的确定性挖掘点。 当线被中断时，所测量的耦合电容是单个导电支路的电容。 互连线的中断的点的位置是确定的，通过测量线的所有段的耦合电容与第二导线开采。

公开(公告)号：EP1071133A1

公开(公告)日：2001-01-24

申请号：EP99830468.7

申请日：1999-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Vendrame, Loris ,  Ghezzi, Paolo

IPC: H01L27/105 ,  H01L21/8249

CPC classification number: H01L29/0692 ,  H01L21/8249 ,  H01L29/7322

Abstract: This invention refers to a bipolar transistor obtained by means of a process for CMOS devices of non volatile memories, and in particular to an integrated circuit comprising a vertical transistor at high gain. Besides it refers to a building process of a bipolar transistor obtained by means a process for CMOS devices of non volatile memories. In one embodiment the integrated circuit obtained by means of a process for CMOS devices of non volatile memories comprises a semiconductor substrate (2) having a first type of conductivity, a pMOS transistor formed above said substrate (2), a nMOS transistor formed above said substrate (2), a bipolar transistor (1) comprising: a buried semiconductor layer (4) having a second type of conductivity placed at a prefixed depth from the surface of said bipolar transistor (1), a isolation semiconductor region (5) having a second type of conductivity in direct contact with said buried semiconductor layer (4) and suitable for delimiting a portion of said substrate (2) forming a base region (3), a emitter region (8) of said transistor (1) formed within said base region (3) having a second type of conductivity, a base contact region (6) of said transistor (1) formed within said base region (3) having a first type of conductivity, a collector contact region (7) of said transistor (1) formed within said isolation semiconductor region (5) having a second type of conductivity, characterised in that said base region (3) has a doping concentration included between 10 16 and 10 17 atoms/cm 3 .

Abstract translation: 本发明涉及通过对非易失性存储器的CMOS器件的过程的手段获得的双极型晶体管，并且具体地涉及在集成电路，包括在高增益的垂直晶体管。 除了它是指通过手段获得了一种用于非易失性存储器的CMOS器件的双极晶体管的构建过程。 在一个实施例通过用于非易失性存储器的CMOS器件的工艺的装置获得的集成电路包括基片（2），具有第一导电类型的半导体，PMOS晶体管高于所述衬底（2），一个nMOS管以上所述形成的晶体管来形成 （4）具有第二类型在预先固定深度从（5），其具有所述双极型晶体管（1），一个隔离半导体区域的表面配置导电性的埋半导体层：基板（2），双极晶体管（1）包括 在与所述直接接触的第二导电类型的掩埋半导体层（4）和适于界定所述基板（2）形成一个基极区域（3），一个发射极区（8）。所述的晶体管来形成（1）内的一部分 所述基区（3）具有第二导电类型的，一个基极接触区域，在所述晶体管的（1）形成在所述（3），其具有第一导电类型的基区，集电极接触区（7）的说（6）内 晶体管（1）所形成withi 具有第二型导电性的，DASS所述基区（3）包括了10 <16> 10 <17>原子/厘米<3>之间的掺杂浓度N个所述隔离半导体区域（5）。