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    Clock generator for electrically programmable nonvolatile memory cells
    2.
    发明公开
    Clock generator for electrically programmable nonvolatile memory cells 失效
    时钟用于非易失性的电可编程存储器单元

    公开(公告)号：EP1359592A3

    公开(公告)日：2006-12-20

    申请号：EP03012504.1

    申请日：1995-10-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tassan Caser, Fabio ,  Dellabora, Marco ,  Defendi, Marco

    IPC: G11C16/06 ,  H02M3/07 ,  H03K3/03

    CPC classification number: H02M3/073 ,  G11C16/12 ,  G11C16/30 ,  H02M3/07 ,  H03K3/0315

    Abstract: The present invention relates to a clock generator circuit (7) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2).
    In particular, the clock generator circuit according to the invention comprises a loop (14) of a plurality of primary inverters (15) and secondary inverters (16) supplying clock signals (ck ,ck ,ck ,ck ) on a plurality of outputs (07), each of the primary inverters (15) having an input terminal (I15) connected to an output terminal (016) of a secondary inverter (16) preceding it in the loop (14), and to the ground voltage reference (GND) through a MOS transistor (N1) controlled by a secondary control signal (PROGN) which corresponds to the negated control signal (PROG), in parallel with a capacitor (C), and having an output terminal (015) connected to a first input (A) of the secondary inverter (16) lying next to it in the loop (14), and to one of the output terminals (07)
    The invention also concerns a charge pump circuit and a phase generator (9) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2) as well as to a three-terminal capacitor.

    Clock generator for electrically programmable nonvolatile memory cells
    6.
    发明公开
    Clock generator for electrically programmable nonvolatile memory cells 失效
    Tak en en ch en en en en en en en en en en

    公开(公告)号：EP1359592A2

    公开(公告)日：2003-11-05

    申请号：EP03012504.1

    申请日：1995-10-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tassan Caser, Fabio ,  Dellabora, Marco ,  Defendi, Marco

    IPC: G11C16/32 ,  G11C16/10 ,  H02M3/07

    CPC classification number: H02M3/073 ,  G11C16/12 ,  G11C16/30 ,  H02M3/07 ,  H03K3/0315

    Abstract: The present invention relates to a clock generator circuit (7) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2).
    In particular, the clock generator circuit according to the invention comprises a loop (14) of a plurality of primary inverters (15) and secondary inverters (16) supplying clock signals (ck ,ck ,ck ,ck ) on a plurality of outputs (07), each of the primary inverters (15) having an input terminal (I15) connected to an output terminal (016) of a secondary inverter (16) preceding it in the loop (14), and to the ground voltage reference (GND) through a MOS transistor (N1) controlled by a secondary control signal (PROGN) which corresponds to the negated control signal (PROG), in parallel with a capacitor (C), and having an output terminal (015) connected to a first input (A) of the secondary inverter (16) lying next to it in the loop (14), and to one of the output terminals (07)
    The invention also concerns a charge pump circuit and a phase generator (9) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2) as well as to a three-terminal capacitor.

    Abstract translation: 本发明涉及一种用于电可编程非易失性存储单元（2）的矩阵阵列的编程电路的时钟发生器电路（7）。 特别地，根据本发明的时钟发生器电路包括多个主反相器（15）的环路（14）和提供时钟信号（ck <1>，ck <2>，ck <3>）的次级反相器（16） ，ck <4>），所述主逆变器（15）中的每一个具有连接到所述环路之前的次级逆变器（16）的输出端子（016）的输入端子（I15） （14）和通过与电容器（C）并联的与否定控制信号（PROG）相对应的次级控制信号（PROGN）控制的MOS晶体管（N1）的接地电压基准（GND），以及 具有连接到位于所述回路（14）中的所述次级逆变器（16）的第二输入端（A）的输出端子（015）和所述输出端子（07）中的一个。本发明还涉及电荷泵 电路和用于电可编程非易失性存储器单元（2）的矩阵阵列的编程电路的相位发生器（9），以及三端 l电容。

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