公开(公告)号：EP1450373A1

公开(公告)日：2004-08-25

申请号：EP03425098.5

申请日：2003-02-21

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Khouri, Osama ,  Resta, Claudio

IPC: G11C11/34 ,  G11C11/56

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A phase change memory (20) has an array (1) formed by a plurality of cells (2), each including a memory element (3) of calcogenic material and a selection element (4) connected in series to the memory element; a plurality of address lines (11) connected to the cells; a write stage (24) and a reading stage (25) connected to the array. The write stage (24) is formed by current generators (45), which supply preset currents to the selected cells (2) so as to modify the resistance of the memory element (3). Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract translation: 相变存储器（20）具有由多个单元（2）形成的阵列（1），每个单元包括煅烧材料的存储元件（3）和与存储元件串联连接的选择元件（4）。 连接到所述单元的多个地址线（11） 写入级（24）和与阵列连接的读取级（25）。 写入级（24）由电流发生器（45）形成，电流发生器（45）向所选择的单元（2）提供预设电流，以便改变存储元件（3）的电阻。 通过适当地偏置所选择的单元并将其中流动的电流与参考值进行比较，读取以电压进行。

公开(公告)号：EP1548745B1

公开(公告)日：2008-10-22

申请号：EP04106858.6

申请日：2004-12-22

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

IPC: G11C11/34 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C8/08

公开(公告)号：EP1548745A1

公开(公告)日：2005-06-29

申请号：EP04106858.6

申请日：2004-12-22

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

IPC: G11C11/34 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C8/08

Abstract: A memory device having a reading configuration and including a plurality of memory cells (3), arranged in rows and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V DD ); a column addressing circuit (4) and a row addressing circuit (5) for respectively addressing a bit line (12) and a word line (13) corresponding to a memory cell (3) selected for reading in the reading configuration. The column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the selected memory cell (3) substantially at the supply voltage (V DD ) in the reading configuration. A row driving circuit (6) biases the addressed word line (13) corresponding to the selected memory cell (3) at a non-zero word line read voltage (V WL ), so that a predetermined cell voltage (V CELL ), lower than a phase change voltage (V PHC ), is applied between the first terminal (3a) and the second terminal (3b) of the selected memory cell (3) in the reading configuration.

Abstract translation: 具有读取配置和包含存储单元的多个（3），以行和列排列的存储器单元的存储器装置（3）布置在具有连接到相同的位线respectivement第一端子（3a）中同一列（12）中 和存储单元（3），布置在同一行上具有respectivement第二端子（3b）中选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VDD）; 一列寻址电路（4）和用于分别寻址的位线（12）和字线（13）的行寻址电路（5）对应于一个存储单元（3）选择用于在读取配置读取。 列寻址电路（4）被配置为偏置对应于所选择的存储单元的寻址位线（12）（3）在基本上在读取配置中的电源电压（VDD）。 行驱动电路（6）偏压对应于所述选定存储器单元被寻址的字线（13）（3）在非零字线读取电压（VWL），所以没有在预定的电池电压（V电池），比下 相变电压（VPHC）在第一端（3a）和在读取配置所述选定存储器单元（3）的第二端（3b）的之间。

公开(公告)号：EP1450373B1

公开(公告)日：2008-08-27

申请号：EP03425098.5

申请日：2003-02-21

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Khouri, Osama ,  Resta, Claudio

IPC: G11C11/34 ,  G11C11/56

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

公开(公告)号：EP1420412B1

公开(公告)日：2008-07-09

申请号：EP02425706.5

申请日：2002-11-18

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Resta, Claudio

IPC: G11C11/34

CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

公开(公告)号：EP1548744A1

公开(公告)日：2005-06-29

申请号：EP03425820.2

申请日：2003-12-23

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

IPC: G11C11/34 ,  G11C8/10

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

Abstract: A memory device includes a plurality of memory cells (3), arranged in row and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V A ); a column addressing circuit (4) for addressing a bit line (12) corresponding to a memory cell (3) to be read; and a row addressing circuit (5) for addressing a word line (13) corresponding to the memory cell (3) to be read. Moreover, the column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the memory cell (3) to be read substantially at the supply voltage (V A ).

Abstract translation: 一种存储器装置包括布置在具有连接到相同的位线（12）和存储单元respectivement第一端子（3a）中同一列的存储单元的多个（3），以行和列排列的存储器单元（3）（3 ）布置在具有respectivement第二端子在同一行（3B）选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VA）; 用于寻址对应于存储单元（3）要被读出的位线（12）的柱寻址电路（4）; 和要被读取用于寻址对应于存储单元（3）的字线（13）的行寻址电路（5）。 更完了，列寻址电路（4）被配置成偏置相应于存储单元（3）被寻址的位线（12）被在电源电压（VA）基本上读取。

公开(公告)号：EP1420412A1

公开(公告)日：2004-05-19

申请号：EP02425706.5

申请日：2002-11-18

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Resta, Claudio

IPC: G11C11/34

CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor (20) of chalcogenic material furnishing an electrical quantity (V(T), I(T)) that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed (21) so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor (20) has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Abstract translation: 一种相变存储器包括：具有与具有相同法律作为一种相变存储元件温度的电阻变化的温度传感器。 温度传感器由电量的硫族化物材料的家具的电阻器（20）所形成（V（T），I（T））做再现相变存储单元和温度的电阻之间的关系; 电量进行处理（21），以便产生参考量所必需的写入和读出的存储器单元。 硫属化物的电阻（20）具有相同的结构的存储单元和被编程有精度，最好是在复位状态。

公开(公告)号：EP1511042A1

公开(公告)日：2005-03-02

申请号：EP03077667.8

申请日：2003-08-27

Applicant: STMicroelectronics S.r.l.

Inventor： Bedeschi, Ferdinando ,  Resta, Claudio

IPC: G11C11/34

CPC classification number: G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

Abstract: A memory device (100) is proposed. The memory device includes a matrix (105) of memory cells (P h,k ,T h,k ) arranged in a plurality of rows and a plurality of columns, each memory cell including a functional element (P h,k ) with a programmable resistivity and a unidirectional conduction access element (T h,k ) connected in series, a plurality of word lines (WL h ) and a plurality of bit lines (BL k ), the memory cells of each row being connected to a corresponding word line and the memory cells of each column being connected to a corresponding bit line, means (120) for driving the bit lines to a desired voltage, means (110c,115) for selecting at least one bit line in an operative condition of the memory device, each selected bit line being connected to the means for driving and each deselected bit line being disconnected from the means for driving, and means (110r) for selecting a word line in the operative condition, each access element associated with the selected word line and the at least one selected bit line being forward biased and the other access elements being reverse biased; the memory device further includes means (Pd h ,Td h ;B k ,Bd,205,S k ,Sd;D k ,Dd,303-320) for biasing the deselected bit lines in the operative condition to prevent a leakage current of the reverse biased access elements from forward biasing the access elements associated with the selected word line and the deselected bit lines.

Abstract translation: 提出了一种存储装置（100）。 存储器件包括排列成多行和多列的存储单元（Ph，k，Th，k）的矩阵（105），每个存储单元包括具有可编程电阻率的功能元件（Ph，k） 串行连接的单向导通接入元件（Th，k），多个字线（WLh）和多个位线（BLk），每行的存储单元连接到相应的字线，并且存储单元 每列连接到对应的位线，用于将位线驱动到期望电压的装置（120），用于在存储器件的操作状态中选择至少一个位线的装置（110c，115），每个选择的位线 连接到用于驱动的​​装置和每个取消选择的位线与用于驱动的​​装置断开;以及用于在操作状态中选择字线的装置（110r），与所选择的字线和所选择的至少一个所选择的字线相关联的每个存取元件 位线正向b 其他访问元素被反向偏移; 存储器件还包括用于在操作状态下偏置未选位线的装置（Pdh，Tdh; Bk，Bd，205，Sk，Sd; Dk，Dd，303-320），以防止反向偏置访问元件 从正向偏置与所选择的字线和取消选择的位线相关联的存取元件。

公开(公告)号：EP1538632A1

公开(公告)日：2005-06-08

申请号：EP03425728.7

申请日：2003-11-12

Applicant: STMicroelectronics S.r.l. ,  Universita' Degli Studi Di Pavia

Inventor： Bedeschi, Ferdinando ,  Resta, Claudio ,  Torelli, Guido

IPC: G11C11/34 ,  G11C7/12

CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A phase change memory device includes a plurality of PCM cells (3), arranged in rows and columns, PCM cells (3) arranged on the same column being connected to a same bit line (10); a plurality of first selectors (12), each coupled to a respective PCM cell (3); an addressing circuit (4, 5) for selectively addressing at least one of the bit lines (10), one of the first selectors (12), and the PCM cell (3) connected to the addressed bit line (10) and to the addressed first selector (12); and a regulated voltage supply circuit (7, 14, 15), selectively connectable to the addressed bit line (10), for supplying a bit line voltage (V BL ). The bit line voltage (V BL ) is correlated to a first control voltage (V EBA ) on the addressed first selector (12), coupled to the addressed PCM cell (3).

Abstract translation: 一种相变存储器装置包括PCM单元的多个（3），以行和列布置，PCM单元（3）布置在相同的列被连接到相同的位线（10）; 第一选择器的多个（12），每个耦合到respectivement PCM单元（3）; 在用于选择性地寻址所述位线中的至少一个（10）中，第一选择器中的一个（12）和所述PCM单元寻址电路（4,5）（3）连接到所寻址的位线（10）和所述 寻址第一选择器（12）; 和经调节的电压供给电路（7，14，15）选择性地连接到用于供给位线电压（VBL）被寻址的位线（10）。 位线电压（VBL）被关联以在被寻址第一选择器（12），耦合到所寻址的PCM单元（3）的第一控制电压（VEBA）。

公开(公告)号：EP1717817A1

公开(公告)日：2006-11-02

申请号：EP05103557.4

申请日：2005-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando

IPC: G11C16/34 ,  G11C16/02

CPC classification number: G11C13/0004 ,  G11C11/22 ,  G11C11/2275 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0083

Abstract: A semiconductor memory device ( 100 ), including a plurality of programmable memory cells ( MC ) each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing ( 115,130,135 ) the memory cells for reading/modifying their status. At least one memory cell ( FMC ) in said plurality is used as detector memory cell, and control means ( 145 ) operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

Abstract translation: 一种半导体存储器件（100），包括多个可编程存储器单元（MC），每个可编程存储器单元适于在至少第一状态和第二状态之间变成一个，所述多个存储器单元包括用于存储数据的存储器单元， 以及用于访问（115,130,135）存储器单元以读取/修改其状态的装置。 所述多个中的至少一个存储单元（FMC）用作检测器存储单元，并且提供与至少一个检测器存储单元可操作地相关联的控制装置（145），所述控制装置用于建立数据的潜在损失 基于所检测到的至少一个检测器存储单元的第一状态存储在所述多个存储单元中。