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    Fast reading, low power consumption memory device and reading method thereof
    2.
    发明公开
    Fast reading, low power consumption memory device and reading method thereof 有权
    存储器阵列具有快速读出操作和更低的功耗和相应的读出方法

    公开(公告)号：EP1548745A1

    公开(公告)日：2005-06-29

    申请号：EP04106858.6

    申请日：2004-12-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C8/10 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C8/08

    Abstract: A memory device having a reading configuration and including a plurality of memory cells (3), arranged in rows and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V DD ); a column addressing circuit (4) and a row addressing circuit (5) for respectively addressing a bit line (12) and a word line (13) corresponding to a memory cell (3) selected for reading in the reading configuration. The column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the selected memory cell (3) substantially at the supply voltage (V DD ) in the reading configuration. A row driving circuit (6) biases the addressed word line (13) corresponding to the selected memory cell (3) at a non-zero word line read voltage (V WL ), so that a predetermined cell voltage (V CELL ), lower than a phase change voltage (V PHC ), is applied between the first terminal (3a) and the second terminal (3b) of the selected memory cell (3) in the reading configuration.

    Abstract translation: 具有读取配置和包含存储单元的多个（3），以行和列排列的存储器单元的存储器装置（3）布置在具有连接到相同的位线respectivement第一端子（3a）中同一列（12）中 和存储单元（3），布置在同一行上具有respectivement第二端子（3b）中选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VDD）; 一列寻址电路（4）和用于分别寻址的位线（12）和字线（13）的行寻址电路（5）对应于一个存储单元（3）选择用于在读取配置读取。 列寻址电路（4）被配置为偏置对应于所选择的存储单元的寻址位线（12）（3）在基本上在读取配置中的电源电压（VDD）。 行驱动电路（6）偏压对应于所述选定存储器单元被寻址的字线（13）（3）在非零字线读取电压（VWL），所以没有在预定的电池电压（V电池），比下 相变电压（VPHC）在第一端（3a）和在读取配置所述选定存储器单元（3）的第二端（3b）的之间。

    Fast reading, low power consumption memory device and reading method thereof
    3.
    发明公开
    Fast reading, low power consumption memory device and reading method thereof 审中-公开
    存储器阵列具有快速读出操作和更低的功耗和相应的读出方法

    公开(公告)号：EP1548744A1

    公开(公告)日：2005-06-29

    申请号：EP03425820.2

    申请日：2003-12-23

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C8/10

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

    Abstract: A memory device includes a plurality of memory cells (3), arranged in row and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V A ); a column addressing circuit (4) for addressing a bit line (12) corresponding to a memory cell (3) to be read; and a row addressing circuit (5) for addressing a word line (13) corresponding to the memory cell (3) to be read. Moreover, the column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the memory cell (3) to be read substantially at the supply voltage (V A ).

    Abstract translation: 一种存储器装置包括布置在具有连接到相同的位线（12）和存储单元respectivement第一端子（3a）中同一列的存储单元的多个（3），以行和列排列的存储器单元（3）（3 ）布置在具有respectivement第二端子在同一行（3B）选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VA）; 用于寻址对应于存储单元（3）要被读出的位线（12）的柱寻址电路（4）; 和要被读取用于寻址对应于存储单元（3）的字线（13）的行寻址电路（5）。 更完了，列寻址电路（4）被配置成偏置相应于存储单元（3）被寻址的位线（12）被在电源电压（VA）基本上读取。

    Voltage regulating circuit for a capacitive load
    6.
    发明公开
    Voltage regulating circuit for a capacitive load 有权
    Spannungsreglerfüreine kapazitive最后

    公开(公告)号：EP1065580A1

    公开(公告)日：2001-01-03

    申请号：EP99830418.2

    申请日：1999-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Micheloni, Rino ,  Motta, Ilaria ,  Torelli, Guido

    IPC: G05F3/02 ,  G05F1/56 ,  G05F3/26 ,  H02J7/16

    CPC classification number: G05F3/242

    Abstract: A voltage regulating circuit for a capacitive load, being connected between first and second terminals of a supply voltage generator (VDD,GND) and having an input terminal (IN) and an output terminal (OUT), comprises an operational amplifier (OP) having an inverting (-) input terminal connected to the input terminal (IN) of the regulating circuit and a non-inverting (+) input terminal connected to an intermediate node of a voltage divider (R1,R2) which is connected between an output node connected to the output terminal (OUT) of the regulating circuit and the second terminal (GND) of the supply voltage generator, and having an output terminal connected, for driving a first field-effect transistor (MPU), between the output node and the first terminal (VDD) of the supply voltage generator, the output terminal of the operational amplifier being further connected to the output node through a compensation network (COMP), and comprises a second field-effect transistor (MPD1) connected between the output node and the second terminal of the supply voltage generator (GND) and having its gate terminal connected to a constant voltage generating circuit means (RB,CB,MB,IB).

    Abstract translation: 一种用于电容性负载的电压调节电路，连接在电源电压发生器（VDD，GND）的第一和第二端子之间并具有输入端（IN）和输出端（OUT），包括运算放大器（OP），其具有 连接到调节电路的输入端子（IN）的反相（ - ）输入端子和连接到分压器（R1，R2）的中间节点的非反相（+）输入端子，其连接在输出节点 连接到调节电路的输出端子（OUT）和电源电压发生器的第二端子（GND），并且具有用于驱动第一场效应晶体管（MPU）的输出端子连接在输出节点和 电源电压发生器的第一端子（VDD），运算放大器的输出端子通过补偿网络（COMP）进一步连接到输出节点，并且包括一个与之相连的第二场效应晶体管（MPD1） 在电源电压发生器（GND）的输出节点和第二端子上，并且其栅极端子连接到恒定电压发生电路装置（RB，CB，MB，IB）。

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