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    Phase change memory device
    1.
    发明公开
    Phase change memory device 有权
    Phasenwechselspeicheranordnung

    公开(公告)号：EP1450373A1

    公开(公告)日：2004-08-25

    申请号：EP03425098.5

    申请日：2003-02-21

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Resta, Claudio

    IPC: G11C11/34 ,  G11C11/56

    CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: A phase change memory (20) has an array (1) formed by a plurality of cells (2), each including a memory element (3) of calcogenic material and a selection element (4) connected in series to the memory element; a plurality of address lines (11) connected to the cells; a write stage (24) and a reading stage (25) connected to the array. The write stage (24) is formed by current generators (45), which supply preset currents to the selected cells (2) so as to modify the resistance of the memory element (3). Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

    Abstract translation: 相变存储器（20）具有由多个单元（2）形成的阵列（1），每个单元包括煅烧材料的存储元件（3）和与存储元件串联连接的选择元件（4）。 连接到所述单元的多个地址线（11） 写入级（24）和与阵列连接的读取级（25）。 写入级（24）由电流发生器（45）形成，电流发生器（45）向所选择的单元（2）提供预设电流，以便改变存储元件（3）的电阻。 通过适当地偏置所选择的单元并将其中流动的电流与参考值进行比较，读取以电压进行。

    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations
    2.
    发明公开
    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权
    非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-

    公开(公告)号：EP1326258A3

    公开(公告)日：2004-10-13

    申请号：EP02028616.7

    申请日：2002-12-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24 ,  G11C16/02

    CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C7/22 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2216/22

    Abstract: A nonvolatile memory device (10'; 10") is described comprising a memory array (11), a row decoder (12) and a column selector (13) for addressing the memory cells (16) of the memory array (11), and a biasing stage (22; 36, 28) for biasing the array access device terminal of the addressed memory cell (16). The biasing stage (22; 36 28) is arranged between the column selector (13) and the memory array (11) and comprises a biasing transistor (22; 36) having a drain terminal connected to the column selector (13), a source terminal connected to the array access device terminal of the addressed memory cell (16), and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block (31) and an output buffer (32) cascaded together. The output buffer (32) may be supplied with either a read voltage (VREAD) or a program voltage (VPROG) supplied by a multiplexer (33). The biasing transistor (22; 36) may be either included as part of the column selector (13) and formed by the selection transistor (22) which is closest to the addressed memory cell (16) or distinct from the selection transistors (20, 21, 22) of the column selector (13).

    Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices
    5.
    发明公开
    Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices 有权
    和用于chalcogenische元件，特别是相变存储器元件的Tempeaturüberwachung电路布置

    公开(公告)号：EP1420412A1

    公开(公告)日：2004-05-19

    申请号：EP02425706.5

    申请日：2002-11-18

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Resta, Claudio

    IPC: G11C11/34

    CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

    Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor (20) of chalcogenic material furnishing an electrical quantity (V(T), I(T)) that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed (21) so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor (20) has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

    Abstract translation: 一种相变存储器包括：具有与具有相同法律作为一种相变存储元件温度的电阻变化的温度传感器。 温度传感器由电量的硫族化物材料的家具的电阻器（20）所形成（V（T），I（T））做再现相变存储单元和温度的电阻之间的关系; 电量进行处理（21），以便产生参考量所必需的写入和读出的存储器单元。 硫属化物的电阻（20）具有相同的结构的存储单元和被编程有精度，最好是在复位状态。

    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations
    6.
    发明公开
    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权
    非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-

    公开(公告)号：EP1326258A2

    公开(公告)日：2003-07-09

    申请号：EP02028616.7

    申请日：2002-12-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24

    CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C7/22 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2216/22

    Abstract: A nonvolatile memory device (10'; 10") is described comprising a memory array (11), a row decoder (12) and a column selector (13) for addressing the memory cells (16) of the memory array (11), and a biasing stage (22; 36, 28) for biasing the array access device terminal of the addressed memory cell (16). The biasing stage (22; 36 28) is arranged between the column selector (13) and the memory array (11) and comprises a biasing transistor (22; 36) having a drain terminal connected to the column selector (13), a source terminal connected to the array access device terminal of the addressed memory cell (16), and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block (31) and an output buffer (32) cascaded together. The output buffer (32) may be supplied with either a read voltage (VREAD) or a program voltage (VPROG) supplied by a multiplexer (33). The biasing transistor (22; 36) may be either included as part of the column selector (13) and formed by the selection transistor (22) which is closest to the addressed memory cell (16) or distinct from the selection transistors (20, 21, 22) of the column selector (13).

    Abstract translation: 一种非易失性存储器装置（10”，10“）被描述为包括用于寻址所述存储器阵列的所述存储器单元（16）的存储器阵列（11），行译码器（12）和列选择器（13）（11） 用于偏压被寻址的存储器单元的阵列接入设备终端（16）的偏置级（22; 36 28）;以及偏压级（36，28 22）。在所述列选择器（13）和存储器阵列（之间布置 11）和包括偏压晶体管（22; 36），具有连接到列选择器（13），连接到所述寻址的存储器单元（16）的阵列存取装置端子的源极端子的漏极端子和栅极端子接收 逻辑驱动信号时，逻辑电平在此通过精确且稳定的电压定义的和由一个逻辑块（31）产生并输出缓冲器（32）级联在一起，输出缓冲器（32）可以与任一个读取电压提供 （VREAD）或编程电压（VPROG）通过一个多路复用器（33）的偏置晶体管提供（22; 36）。可以是eithe ř包括作为列选择器（13）的一部分，并且由选择晶体管（22），所有这些是最近的到所寻址的存储器单元（16）或不同从列选择器的选择晶体管（20，21，22）而形成（13 ）。

    Single supply voltage nonvolatile memory device with hierarchical row decoding
    10.
    发明公开
    Single supply voltage nonvolatile memory device with hierarchical row decoding 有权
    Einzige SpeisespannungsschaltungfürnichtflüchtigenSpeicher mit hierarchicalischem Reihendekodierer

    公开(公告)号：EP1073060A1

    公开(公告)日：2001-01-31

    申请号：EP99830483.6

    申请日：1999-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Sacco, Andrea ,  Picca, Massimiliano

    IPC: G11C8/00

    CPC classification number: G11C5/145 ,  G11C5/14 ,  G11C8/10

    Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).

    Abstract translation: 存储器件（10）包括具有包括全局字线（4）和本地字线（6）类型的组织的存储器阵列（2），寻址全局字线（4）的全局行解码器（8） 寻址本地字线（6）的本地行解码器（12），提供全局行解码器（8）的全局电源级（22）和提供本地行解码器（12）的本地电源级（24） 。

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