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1.发明授权Fast reading, low power consumption memory device and reading method thereof 有权存储器阵列具有快速读出操作和更低的功耗和相应的读出方法
公开(公告)号：EP1548745B1
公开(公告)日：2008-10-22
申请号：EP04106858.6
申请日：2004-12-22
Applicant: STMicroelectronics S.r.l. , Ovonyx Inc.
Inventor： Resta, Claudio , Bedeschi, Ferdinando , Torelli, Guido
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2.发明公开Fast reading, low power consumption memory device and reading method thereof 有权存储器阵列具有快速读出操作和更低的功耗和相应的读出方法
公开(公告)号：EP1548745A1
公开(公告)日：2005-06-29
申请号：EP04106858.6
申请日：2004-12-22
Applicant: STMicroelectronics S.r.l. , Ovonyx Inc.
Inventor： Resta, Claudio , Bedeschi, Ferdinando , Torelli, Guido
Abstract: A memory device having a reading configuration and including a plurality of memory cells (3), arranged in rows and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V DD ); a column addressing circuit (4) and a row addressing circuit (5) for respectively addressing a bit line (12) and a word line (13) corresponding to a memory cell (3) selected for reading in the reading configuration. The column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the selected memory cell (3) substantially at the supply voltage (V DD ) in the reading configuration. A row driving circuit (6) biases the addressed word line (13) corresponding to the selected memory cell (3) at a non-zero word line read voltage (V WL ), so that a predetermined cell voltage (V CELL ), lower than a phase change voltage (V PHC ), is applied between the first terminal (3a) and the second terminal (3b) of the selected memory cell (3) in the reading configuration.
Abstract translation: 具有读取配置和包含存储单元的多个（3），以行和列排列的存储器单元的存储器装置（3）布置在具有连接到相同的位线respectivement第一端子（3a）中同一列（12）中 和存储单元（3），布置在同一行上具有respectivement第二端子（3b）中选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VDD）; 一列寻址电路（4）和用于分别寻址的位线（12）和字线（13）的行寻址电路（5）对应于一个存储单元（3）选择用于在读取配置读取。 列寻址电路（4）被配置为偏置对应于所选择的存储单元的寻址位线（12）（3）在基本上在读取配置中的电源电压（VDD）。 行驱动电路（6）偏压对应于所述选定存储器单元被寻址的字线（13）（3）在非零字线读取电压（VWL），所以没有在预定的电池电压（V电池），比下 相变电压（VPHC）在第一端（3a）和在读取配置所述选定存储器单元（3）的第二端（3b）的之间。
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3.发明公开Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-
公开(公告)号：EP1326258A3
公开(公告)日：2004-10-13
申请号：EP02028616.7
申请日：2002-12-20
Applicant: STMicroelectronics S.r.l. , OVONYX Inc.
Inventor： Khouri, Osama , Bedeschi, Ferdinando
CPC classification number: G11C11/5678 , G11C7/04 , G11C7/22 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2216/22
Abstract: A nonvolatile memory device (10'; 10") is described comprising a memory array (11), a row decoder (12) and a column selector (13) for addressing the memory cells (16) of the memory array (11), and a biasing stage (22; 36, 28) for biasing the array access device terminal of the addressed memory cell (16). The biasing stage (22; 36 28) is arranged between the column selector (13) and the memory array (11) and comprises a biasing transistor (22; 36) having a drain terminal connected to the column selector (13), a source terminal connected to the array access device terminal of the addressed memory cell (16), and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block (31) and an output buffer (32) cascaded together. The output buffer (32) may be supplied with either a read voltage (VREAD) or a program voltage (VPROG) supplied by a multiplexer (33). The biasing transistor (22; 36) may be either included as part of the column selector (13) and formed by the selection transistor (22) which is closest to the addressed memory cell (16) or distinct from the selection transistors (20, 21, 22) of the column selector (13).
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4.发明授权Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices 有权和用于chalcogenische元件，特别是相变存储器元件的Tempeaturüberwachung电路布置
公开(公告)号：EP1420412B1
公开(公告)日：2008-07-09
申请号：EP02425706.5
申请日：2002-11-18
Applicant: STMicroelectronics S.r.l. , Ovonyx Inc.
Inventor： Khouri, Osama , Bedeschi, Ferdinando , Resta, Claudio
IPC: G11C11/34
CPC classification number: G11C7/04 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2029/5002 , G11C2213/79
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5.发明公开Fast reading, low power consumption memory device and reading method thereof 审中-公开存储器阵列具有快速读出操作和更低的功耗和相应的读出方法
公开(公告)号：EP1548744A1
公开(公告)日：2005-06-29
申请号：EP03425820.2
申请日：2003-12-23
Applicant: STMicroelectronics S.r.l. , OVONYX Inc.
Inventor： Resta, Claudio , Bedeschi, Ferdinando , Torelli, Guido
CPC classification number: G11C13/0004 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004
Abstract: A memory device includes a plurality of memory cells (3), arranged in row and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V A ); a column addressing circuit (4) for addressing a bit line (12) corresponding to a memory cell (3) to be read; and a row addressing circuit (5) for addressing a word line (13) corresponding to the memory cell (3) to be read. Moreover, the column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the memory cell (3) to be read substantially at the supply voltage (V A ).
Abstract translation: 一种存储器装置包括布置在具有连接到相同的位线（12）和存储单元respectivement第一端子（3a）中同一列的存储单元的多个（3），以行和列排列的存储器单元（3）（3 ）布置在具有respectivement第二端子在同一行（3B）选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VA）; 用于寻址对应于存储单元（3）要被读出的位线（12）的柱寻址电路（4）; 和要被读取用于寻址对应于存储单元（3）的字线（13）的行寻址电路（5）。 更完了，列寻址电路（4）被配置成偏置相应于存储单元（3）被寻址的位线（12）被在电源电压（VA）基本上读取。
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Patent Agency Ranking6.发明公开Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices 有权和用于chalcogenische元件，特别是相变存储器元件的Tempeaturüberwachung电路布置
公开(公告)号：EP1420412A1
公开(公告)日：2004-05-19
申请号：EP02425706.5
申请日：2002-11-18
Applicant: STMicroelectronics S.r.l. , OVONYX Inc.
Inventor： Khouri, Osama , Bedeschi, Ferdinando , Resta, Claudio
IPC: G11C11/34
CPC classification number: G11C7/04 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2029/5002 , G11C2213/79
Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor (20) of chalcogenic material furnishing an electrical quantity (V(T), I(T)) that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed (21) so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor (20) has the same structure as a memory cell and is programmed with precision, preferably in the reset state.
Abstract translation: 一种相变存储器包括：具有与具有相同法律作为一种相变存储元件温度的电阻变化的温度传感器。 温度传感器由电量的硫族化物材料的家具的电阻器（20）所形成（V（T），I（T））做再现相变存储单元和温度的电阻之间的关系; 电量进行处理（21），以便产生参考量所必需的写入和读出的存储器单元。 硫属化物的电阻（20）具有相同的结构的存储单元和被编程有精度，最好是在复位状态。
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7.发明公开Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-
公开(公告)号：EP1326258A2
公开(公告)日：2003-07-09
申请号：EP02028616.7
申请日：2002-12-20
Applicant: STMicroelectronics S.r.l. , OVONYX Inc.
Inventor： Khouri, Osama , Bedeschi, Ferdinando
IPC: G11C16/24
CPC classification number: G11C11/5678 , G11C7/04 , G11C7/22 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2216/22
Abstract: A nonvolatile memory device (10'; 10") is described comprising a memory array (11), a row decoder (12) and a column selector (13) for addressing the memory cells (16) of the memory array (11), and a biasing stage (22; 36, 28) for biasing the array access device terminal of the addressed memory cell (16). The biasing stage (22; 36 28) is arranged between the column selector (13) and the memory array (11) and comprises a biasing transistor (22; 36) having a drain terminal connected to the column selector (13), a source terminal connected to the array access device terminal of the addressed memory cell (16), and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block (31) and an output buffer (32) cascaded together. The output buffer (32) may be supplied with either a read voltage (VREAD) or a program voltage (VPROG) supplied by a multiplexer (33). The biasing transistor (22; 36) may be either included as part of the column selector (13) and formed by the selection transistor (22) which is closest to the addressed memory cell (16) or distinct from the selection transistors (20, 21, 22) of the column selector (13).
Abstract translation: 一种非易失性存储器装置（10”，10“）被描述为包括用于寻址所述存储器阵列的所述存储器单元（16）的存储器阵列（11），行译码器（12）和列选择器（13）（11） 用于偏压被寻址的存储器单元的阵列接入设备终端（16）的偏置级（22; 36 28）;以及偏压级（36，28 22）。在所述列选择器（13）和存储器阵列（之间布置 11）和包括偏压晶体管（22; 36），具有连接到列选择器（13），连接到所述寻址的存储器单元（16）的阵列存取装置端子的源极端子的漏极端子和栅极端子接收 逻辑驱动信号时，逻辑电平在此通过精确且稳定的电压定义的和由一个逻辑块（31）产生并输出缓冲器（32）级联在一起，输出缓冲器（32）可以与任一个读取电压提供 （VREAD）或编程电压（VPROG）通过一个多路复用器（33）的偏置晶体管提供（22; 36）。可以是eithe ř包括作为列选择器（13）的一部分，并且由选择晶体管（22），所有这些是最近的到所寻址的存储器单元（16）或不同从列选择器的选择晶体管（20，21，22）而形成（13 ）。
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8.发明授权Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-
公开(公告)号：EP1326258B1
公开(公告)日：2016-03-23
申请号：EP02028616.7
申请日：2002-12-20
Applicant: STMicroelectronics Srl , Ovonyx Inc.
Inventor： Khouri, Osama , Bedeschi, Ferdinando
CPC classification number: G11C11/5678 , G11C7/04 , G11C7/22 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2216/22
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9.发明公开Phase-change memory device with error correction capability 审中-公开Phasenwechsel-Speichervorrichtung mit Fehlerkorrekturfunktion
公开(公告)号：EP1947652A1
公开(公告)日：2008-07-23
申请号：EP07425569.6
申请日：2007-09-13
Applicant: STMicroelectronics S.r.l.
Inventor： Donze, Enzo Michele , Bedeschi, Ferdinando , Jagasivamani, Meenatchi
CPC classification number: B01F7/04 , B01F7/00258 , B01F7/00425 , B01F13/06 , B01F2015/0221 , G06F11/1068 , G11C13/02
Abstract: A phase-change memory device includes a plurality of data PCM cells (13), for storing data bits; data decoding circuits (14, 27, 28a), for selectively addressing sets of data PCM cells (13); and data read/program circuits (20a), for reading and programming the selected data PCM cells (13). The device further includes a plurality of parity PCM cells (25), for storing parity bits associated to data bits stored in the data PCM cells (13); parity decoding circuits (14, 27, 28b), for selectively addressing sets of parity PCM cells (25); and parity read/program circuits (20b), for reading and programming the selected parity PCM cells (25).
Abstract translation: 相变存储器件包括用于存储数据位的多个数据PCM单元（13）; 数据解码电路（14,27,28a），用于选择性寻址数据PCM单元（13）; 和数据读取/编程电路（20a），用于读取和编程所选择的数据PCM单元（13）。 该装置还包括多个奇偶校验PCM单元（25），用于存储与存储在数据PCM单元（13）中的数据位相关联的奇偶校验位; 奇偶校验解码电路（14,27,28b），用于选择性地寻址奇偶校验PCM单元（25）组; 以及用于读取和编程所选奇偶校验PCM单元（25）的奇偶校验读/写电路（20b）。
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10.发明公开A memory device with unipolar and bipolar selectors 有权Speiherannnung mit unipolaren和bipolaren Auswahlschaltungen
公开(公告)号：EP1640994A1
公开(公告)日：2006-03-29
申请号：EP04104595.6
申请日：2004-09-22
Applicant: STMicroelectronics S.r.l.
Inventor： Bedeschi, Ferdinando , Pellizzer, Fabio , Benvenuti, Augusto , Vendrame, Loris , Zuliani, Paola
CPC classification number: G11C13/0004 , G11C13/003 , G11C2213/76 , G11C2213/79
Abstract: A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.
Abstract translation: 提出了一种存储器件。 存储器件包括多个存储器单元（P，S），其中每个存储器单元包括用于在读取操作或编程操作期间选择相应的存储元件的存储元件（P）和选择器（S）。 选择器包括单极元件（M）和双极元件（D; B）。 存储器件还包括控制装置（110s），用于在编程操作期间在读取操作期间使单极元件能够被普遍使能或双极元件。
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