Abstract:
A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.
Abstract:
Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.
Abstract:
The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.
Abstract:
A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.
Abstract:
Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.
Abstract:
Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.
Abstract:
A semiconductor device includes: a substrate including an active pattern; a first channel structure overlapping the active pattern; a gate electrode including an electrode portion between the active pattern and the first channel structure; a semiconductor layer contacting the first channel structure; and a source/drain pattern contacting the first channel structure, wherein the first channel structure includes: a first upper channel layer; a first lower channel layer; and a first intervening channel layer disposed between the first upper channel layer and the first lower channel layer, wherein the semiconductor layer contacts a sidewall of the first upper channel layer, a sidewall of the first lower channel layer, and a sidewall of the first intervening channel layer, and wherein the semiconductor layer and the first intervening channel layer include a semiconductor material that is different from a semiconductor material of the first upper channel layer and the first lower channel layer.
Abstract:
A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.
Abstract:
A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.
Abstract:
Disclosed is a semiconductor device. The semiconductor device comprises a fin structure on a substrate, device isolation patterns provided on the substrate and disposed on opposite sides of the fin structure, a gate electrode running across the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and a capping layer between the substrate and the device isolation patterns and between the fin structure and the device isolation patterns. The capping layer has a thickness greater than a thickness of the gate dielectric pattern.