公开(公告)号：JPH06208477A

公开(公告)日：1994-07-26

申请号：JP40589990

申请日：1990-12-25

Applicant: TANDEM COMPUTERS INC

Inventor： DAGURASU II JIYUETSUTO ,  TOMU BEREITAA ,  BURAIAN BUETAA ,  RANDARU JII BANTON ,  RICHIYAADO DABURIYU KATSUTSU J ,  DONARUDO SHII UESUTOBURUTSUKU ,  KIRAN DABURIYU FUEI JIYUNIA ,  JIYON POZUROO ,  KENESU SHII DOUBATSUKAA ,  NIKUHERU EI MEETA ,  FUIRU UEBUSUTAA ,  DEIBU ARUDORITSUJI ,  PIITAA SHII NOOUTSUDO

IPC: G06F1/30 ,  G06F11/00 ,  G06F11/14 ,  G06F11/18 ,  G06F11/22 ,  G06F12/16 ,  G06F15/16

Abstract: PURPOSE: To improve the reliability of a fault-tolerant computer by securing the operating ability of the computer at a high level by detecting the component of a system which gets out of order and setting the component in an off-line state so that the component can be reincorporated without shutting down the system. CONSTITUTION: A system is provided with a plurality of CPUs 11, 12, and 13 which execute the same instruction stream and each CPU is provided with a local memory 16 and operated to access a plurality of global memories 14 and 15. When, for example, the error of one CPU 11 is detected, the CPU 11 is isolated from the system and the execution of the instruction stream is continued, and then, the operation is continued by accessing the memories 14 and 15 from the other CPUs 12 and 13. When the CPU 11 is remedied, the CPU 11 is first made to be operable by synchronizing the CPU 11 to the CPUs 12 and 13, and then, the CPU 11 is restored so that the state and local memory 16 of the CPU 11 can become the same as those of the CPUs 12 and 13.

公开(公告)号：JPH02202636A

公开(公告)日：1990-08-10

申请号：JP32246189

申请日：1989-12-11

Applicant: TANDEM COMPUTERS INC

Inventor： RICHIYAADO DABURIYUU KATSUTSU ,  RANDARU JII BANTON ,  DAGURASU II JIYUUETSUTO ,  PIITAA SHII NOOUTSUDO ,  KENISU SHII DEIBETSUKAA ,  NIKIIRU EE MEETA ,  JIYON DEIBITSUDO ARISON ,  ROBAATO TABURIYUU HOOSUTO

IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

Abstract: PURPOSE: To replace faulty parts without system shutdown by minimizing a porting circuit to separate faulty parts while running the system. CONSTITUTION: When all CPUs 11 to 13 enter the interrupt state, they output the interrupt requests to all memory modules 14 and 15 by individual lines of an interrupt bus 35. When all interrupts are ported, memory modules 14 and 15 transmit the interrupt requests ported to three CPUs 11 to 13 through the bus 35. CPUS 11 to 13 synchronize these ported interrupts with a CPU interrupt signal through an inter-CPU bus 18, and interrupts are indicated to all CPUs 11 to 13 at a common point of an instruction stream.

公开(公告)号：JPH09128347A

公开(公告)日：1997-05-16

申请号：JP14555196

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU EDOWAADO BEIKAA ,  RANDARU JII BANTON ,  JIYON MAIKERU BURAUN ,  UIRIAMU EFU BURUTSUKAATO ,  UIRIAMU PATAASON BANTON ,  GEARII EFU KIYANBERU ,  JIYON DEIIN KOODEINTON ,  RICHIYAADO DABURIYUU KATSUTSU ,  BARII RII DOREKUSURAA ,  HARII FURANKU ERUROTSUDO ,  DANIERU ERU FUAURAA ,  DEIBUITSUDO JIEI GAASHIA ,  POORU ENU HINTEITSUKA ,  JIEFURII AI ISUWANDEII ,  DAGURASU YUUJIIN JIYUUITSUTO ,  KAATEISU UIIRAADO JIYOONZU JIY ,  JIEEMUZU SUTEIIBUNSU KURETSUKA ,  JIYON SHII KURAUSU ,  SUTEIIBUN JII ROU ,  SUUZAN SUTOON MERADEISU ,  SUTEIIBUN SHII MEIAAZU ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  PATORISHIA ERU HOWAITOSAIDO ,  FURANKU EI UIRIAMUSU ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G06F11/16 ,  G06F15/16 ,  G06F15/17

Abstract: PROBLEM TO BE SOLVED: To facilitate fault-tolerant operation by including a routing element coupled with the central processor and peripheral device of a subprocessing system so as to transmit data between the central processor and peripheral device of the subprocessing system. SOLUTION: Subprocessor systems 10A and 10B include central processors CPUs 12, routers 14, and plural input/output I/O packet interfaces 16 connected to many I/O devices 17 by characteristic input/output NIO buses. The MPs 18 of the subprocessor system 10A and 10B connect IEEE1149. one-test buses 17 and registers used by the MPs 18 to transmit states and control information between elements and MPs 18 to elements of the subprocessor systems through on-line access port OLAP interfaces included in the elements.