公开(公告)号：JP2004077670A

公开(公告)日：2004-03-11

申请号：JP2002236053

申请日：2002-08-13

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KIYOTA TOSHIYA ,  TSUTSUMI JUNSEI ,  KAMATA YOSHITAKA

IPC: G02F1/1368 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a liquid crystal display device with improved characteristics. SOLUTION: A semiconductor layer 8 of a thin film transistor (TFT) 7 and one electrode 10 of an auxiliary capacitance 9 are formed. A gate insulating film 11 containing a capacitance region 12 is formed on the semiconductor layer 8 and the one electrode 10. An impurity is doped into the semiconductor layer 8 and the one electrode 10 of the auxiliary capacitance 9 via the gate insulating film 11 so as to make the one electrode 10 metal-like. After doping of the impurity a surface of the gate insulating film 11 is removed. A gate electrode 19 and the other electrode 20 are formed via the gate insulating film 11. As any damage on the surface of the gate insulating film 11 is removed, slowdown of a voltage between a gate and a source due to variation of a bias voltage gets smaller, steepness of rise is increased. At the same time, as the TFT is certainly insulated with the gate insulating film 11, the TFT efficiently operates and consequently power consumption is suppressed. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002289863A

公开(公告)日：2002-10-04

申请号：JP2001089609

申请日：2001-03-27

Applicant: TOSHIBA CORP

Inventor： TSUTSUMI JUNSEI ,  KIYOTA TOSHIYA ,  TORIYAMA SHIGETAKA ,  KADO MASATERU

IPC: G02F1/1333 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an array substrate that prevents the step-disconnection of wiring, improves the shape of wiring, prevents a resistance rise resulting from the oxidation of wiring and electrode materials caused in annealing step and also the occurrence of stray current corrosion with an ITO, and to provide a method of manufacturing the substrate and a liquid crystal display element. SOLUTION: The array substrate is provided with thin film transistors provided at every intersections of a plurality of scanning lines 5, with a plurality of signal lines being formed on a transparent substrate 1, pixel electrodes 10 which receive signals fetched by means of the transistors, and wiring 17 and 10 which is formed on insulation layers 9 and connects the electrodes 10 to their corresponding thin-film transistors. The wiring 17 and 10 is constituted in laminated wiring composed of first metal layers 17 formed on the insulation films 9 and second metal layers 10 formed on the layers 17. The second metal layers 10 contains at least one element selected from among silver, gold, and copper and the first metal layers 17 are constituted of a metal material, which is more easily oxidized than that of the second metal layers 10.

公开(公告)号：JPH08248442A

公开(公告)日：1996-09-27

申请号：JP5229795

申请日：1995-03-13

Applicant: TOSHIBA CORP

Inventor： IKEDA MITSUSHI ,  KIYOTA TOSHIYA

IPC: G02F1/1333 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1368 ,  H01L29/786

Abstract: PURPOSE: To obtain low resistance, high chemical resistance in the succeeding processes and to obtain good adhesion property on a glass substrate which requires low temp. treatment by forming a conductive layer with addition of specified metal and a nitride layer of a second metal to constitute a wiring layer. CONSTITUTION: At least the wiring layer consists of a metal layer essentially comprising at least one kind of first metal selected from Cu, Al, Ag, Au, Pt with addition of at least one kind of second metal selected from Ti, Zr, Hf, Al, Ta, Si, B, and a second metal nitride layer which covers the surface of the metal layer. Namely, for example, the gate electrode wire 17a consists of a Cu-Zr alloy conductive layer 20a and a ZrN nitride layer 21a which covers the conductive layer 20a. The ZrN layer 21a is also formed between the conductive layer 20a and a substrate 12. Similarly, the storage capacitor line 19 consists of a Cu-Zr alloy conductive layer 20b and a ZrN insulating layer 21b which covers the conductive layer 20b. Further, the address line is patterned at one time.

公开(公告)号：JPH08166598A

公开(公告)日：1996-06-25

申请号：JP30863194

申请日：1994-12-13

Applicant: TOSHIBA CORP

Inventor： IKEDA TAKAMI ,  AKIYAMA MASAHIKO ,  KIYOTA TOSHIYA ,  IKEDA MITSUSHI

IPC: G02F1/136 ,  G02F1/1368

Abstract: PURPOSE: To lessen light leak current and to lessen the occurrence of deterioration in a display grade occurring in peeling of a light shielding film covering a TFT by specifying the relation between the thickness of the light shielding layer on a channel protective layer and the thickness of the light shielding layer on source and drain regions. CONSTITUTION: The light shielding layer 10 is formed on the TFT 51 at a thickness of 0.5μm

公开(公告)号：JP2003055780A

公开(公告)日：2003-02-26

申请号：JP2001245420

申请日：2001-08-13

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KADO MASATERU ,  KIYOTA TOSHIYA

IPC: C23F1/30

Abstract: PROBLEM TO BE SOLVED: To suppress side etching as far as possible.
SOLUTION: In carrying out etching of laminated films consisting of silver or a silver alloy by using an etching solution consisting of mixed acids composed of a phosphoric acid, nitric acid and acetic acid, the etching solution is made to flow and the flow intensity thereof is specified to a range from the fluid intensity at which the etching reaction starts up to the fluid intensity of 67% thereof.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：尽可能地抑制侧蚀刻。 解决方案：通过使用由磷酸，硝酸和乙酸组成的混合酸组成的蚀刻溶液对由银或银合金构成的叠层膜进行蚀刻，使蚀刻溶液流动，其流动强度为 指定为从蚀刻反应开始的流体强度到其67％的流体强度的范围。

公开(公告)号：JP2000114537A

公开(公告)日：2000-04-21

申请号：JP28569898

申请日：1998-10-07

Applicant: TOSHIBA CORP

Inventor： UEMOTO TSUTOMU ,  KIYOTA TOSHIYA ,  KASHIRO TAKESHI

IPC: H01L29/786 ,  G02F1/136 ,  G02F1/1368

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of CMOS configuration, together with a method for manufacturing it, wherein a desired threshold voltage is set for stable circuit operation. SOLUTION: Related to a semiconductor device comprising p-type and n-type TFTs, a different impurity concentration is separately set for a channel layer of p-type TFT and that of n-type TFT. Thus, the threshold voltages of p-type TFT and n-type TFT come to be optimum values, respectively. A device like this is provided by performing ion-implantation, for example of boron, with an amorphous silicon film 3, and then patterning to form island-like semiconductor films 4a and 4b, and selectively implanting, for example, boron or phosphorous into either of them.

公开(公告)号：JPH10253983A

公开(公告)日：1998-09-25

申请号：JP6147697

申请日：1997-03-14

Applicant: TOSHIBA CORP

Inventor： UEDA TOMOMASA ,  KIYOTA TOSHIYA ,  HIOKI TAKESHI ,  MIZUTANI YOSHIHISA ,  AKIYAMA MASAHIKO

IPC: G02F1/136 ,  G02F1/1368

Abstract: PROBLEM TO BE SOLVED: To provide a reflection type liquid crystal display device that as high in aperture ratio and has a structure capable of being formed by a small number of masking processes. SOLUTION: In this device, plural lines of scanning lines 22 and signal lines are provided in a matrix array shape with thin film transistors 16 on an insulating substrate 1 and reflection pixel electrodes 11 which are processed to be low reflections are used. Since the reflection pixel electrodes 11 can be formed out of the same material as that of the signal lines 23, the number of processes can be also reduced. Moreover, since the reflection pixel electrodes 11 and the signal lines 23 can be patterned with the same process, the need for aligning masks is eliminated and the interval between the reflection pixel electrode 11 and the signal line 23 can be formed narrower to increase the aperture ratio.

公开(公告)号：JPH1093090A

公开(公告)日：1998-04-10

申请号：JP24278596

申请日：1996-09-13

Applicant: TOSHIBA CORP

Inventor： YAMADA HIROSAKU ,  KIYOTA TOSHIYA ,  UCHIKOGA SHIYUUICHI

IPC: G02F1/136 ,  G02F1/1368 ,  H01L21/316 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To enable forming a coating, having a sufficient barrierability, even if a general resin material is used, by forming a semiconductor film in which an active layer for a semiconductor device has been formed, on an inorganic insulating film containing specified impurities on an organic resin substrate. SOLUTION: An acrylic resin substrate containing Na being an alkaline metal of a sufficient concentration is used. First, SiO2 2 of 30nm is deposited on a substrate 1 by 100 deg.C plasma CVD, using SiH4 and N2 O as materials. The formation condition is 120 deg.C. Following this, this substrate 1 is dipped in a 5% NaCl aqueous solution 3, put in a glass container 5 for 48 hours, is washed simply after that, and is dried subsequently to form a plastic substrate sufficiently polluted by Na. An SiO2 film 4 is deposited by 200nm with CVD, similarly to the SiO2 2 forming process. Next, As ions are used and implanted to a specified concentration with an acceleration energy of 40keV, it is possible to obtain a blocking ability with respect to alkaline metals by this coating.

公开(公告)号：JPH07245406A

公开(公告)日：1995-09-19

申请号：JP3514094

申请日：1994-03-07

Applicant: TOSHIBA CORP

Inventor： AKIYAMA MASAHIKO ,  IKEDA TAKAMI ,  KIYOTA TOSHIYA

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786

Abstract: PURPOSE:To provide a thin-film transistor which has a high driving capacity and can operate quickly even if a channel length is reduced. CONSTITUTION:A gate metal 2 is formed on a glass substrate 1. A sate insulation film 3 is formed on the glass substrate 1 and the gate metal 2 and an amorphous silicon layer 4 which becomes a channel region is formed at a position corresponding to the gate metal 2 on it, and ion-implanted amorphous silicon layer 7 which becomes source/drain regions is formed at both sides. A silicon layer 5 containing a crystal which becomes a channel region is formed on the amorphous silicon layer 4 and a silicon layer 8 containing an ion- implanted crystal which becomes source/drain regions is formed at both sides. A channel protection film 6 is formed on the silicon layer 5 containing the crystal.

公开(公告)号：JP2002107760A

公开(公告)日：2002-04-10

申请号：JP2000298464

申请日：2000-09-29

Applicant: TOSHIBA CORP

Inventor： KIYOTA TOSHIYA

IPC: G02F1/13 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/30 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To prevent defects caused by particles in an interlayer insulating film and to improve the yield. SOLUTION: The interlayer insulating film is formed in two steps. After a first interlayer insulating film 13 is formed, brush cleaning is implemented by using a cathode water in the process prior to the formation of a second interlayer insulating film 14. Thereby, leaking caused by particles in the interlayer insulating film can be prevented and the yield can be improved.