公开(公告)号：EP0805614A4

公开(公告)日：1998-11-25

申请号：EP96938496

申请日：1996-11-18

Applicant: TOSHIBA KK

Inventor： SASAOKA KENJI ,  ODAIRA HIROSHI ,  FUJIWARA MADOKA ,  IKEGAYA FUMITOSHI ,  MORI TAKAHIRO

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/095 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09863 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic parts, etc.

公开(公告)号：JPS6030155A

公开(公告)日：1985-02-15

申请号：JP13847583

申请日：1983-07-28

Applicant: TOSHIBA KK

Inventor： SASAOKA KENJI

IPC: H01L23/02 ,  H01L23/04 ,  H01L23/057

Abstract: PURPOSE:To obtain a hybrid integrated circuit module having excellent convertibility in IC chips, superior moisture vapor resistance and high reliability by hermetically sealing the IC chips by mini-caps at every one or several piece and packing the IC chips by molds with a resin. CONSTITUTION:IC chips 1 are mounted onto a substrate 3, the IC chips are hermetically sealed in He or N2 gas in order to prevent the oxidation of the IC chips by mini-caps 7 consisting of plastics, ceramics or the like at every small number such as one or two or three, and the outer surfaces of the mini-caps 7 are packed by molds with a resin 6 and sealed. When a defective IC chip is generated, a mold pack and a hermetic seal on the section of the defective IC chip are removed, and the IC chip can be exchanged easily.

公开(公告)号：JPS60111765A

公开(公告)日：1985-06-18

申请号：JP21912783

申请日：1983-11-21

Applicant: TOSHIBA KK

Inventor： SASAOKA KENJI

IPC: H05K3/24 ,  B23K3/06 ,  H05K3/34

Abstract: PURPOSE:To form a titled solder layer having a desired uniform thickness in a desired part by detecting the heating up of the string solder in contact with the metallized pattern of a circuit board to a prescribed temp. and starting the movement of the circuit board or the wire solder. CONSTITUTION:A circuit board 1 consisting of a composite material plate of ceramics, etc. is heated by a heat transfer plate disposed in the prescribed position of a base plate 6 of a soldering device 8 so as to be maintained in the state adequate for soldering of a solder layer 2. The melt and consumption of string solder 5 are detected by a rotor 9 mounted to a solder supply nozzle 4 and the solder 5 is supplied by the rotor 9. The supply of the solder 5 and the movement of the plate 6 are accomplished by NC control, etc. More specifically, the nozzle 4 is pressed to the metallized pattern 3 of the board 1 and the melt and consumption of the solder 5 are sensed by the rotor 9, the signal thereof is fed to a control device 7. The nozzle 4 is then controlled so as to move along the pattern of the board 1 by motors 10 and 11 which drive the plate 6 in transverse and longitudinal directions respectively, thereby forming the solder layer 2 to the prescribed thickness.

公开(公告)号：JPS6030119A

公开(公告)日：1985-02-15

申请号：JP13847483

申请日：1983-07-28

Applicant: TOSHIBA KK

Inventor： CHIBA KOUICHI ,  TERASAKA YOSHIO ,  SASAOKA KENJI

IPC: H01L21/68 ,  H01L21/02 ,  H01L21/67

Abstract: PURPOSE:To identify patterns accurately and avoid eroneous wire bonding by a method wherein identification marks are provided in or near the bonding pads and bonding positions are determined by the pattern identification of those marks. CONSTITUTION:Near a bonding pad 4 of a group of bonding pads 4 positioned at a far end, an identification mark 7 for pattern identification is provided. The identification mark 7 is provided also near a bonding pad 4 of the bonding pads in a facing row also positioned at the far ends. When a leadframe on a substrate and the bonding pads 4 are wire-bonded with wires such as gold wires, the identification mark 7 provided near the bonding pad 4 formed on a semiconductor pellet 3 is read by a TV camera and the like for pattern identification to determine the bonding position and the leadframe and the bonding pads 4 are wire-bonded by a bonder.

公开(公告)号：JP2918627B2

公开(公告)日：1999-07-12

申请号：JP14299390

申请日：1990-05-30

Applicant: TOSHIBA KK

Inventor： YOSHIDA KENICHI ,  SASAOKA KENJI ,  MORI TAKAHIRO

IPC: H05K3/46