公开(公告)号：US20250167168A1

公开(公告)日：2025-05-22

申请号：US18945569

申请日：2024-11-13

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HunTaek LEE ,  HeeSoo LEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01Q1/22

Abstract: A method for forming an electronic package is provided. The method comprises: providing a package substrate having a front surface and a back surface, wherein multiple sets of conductive pads are formed on the front surface of the package substrate; forming solder bumps on each set of conductive pads; attaching multiple front electronic components onto the front surface of the package substrate via solder bumps, wherein each of the multiple front electronic components is aligned with one set of the multiple sets of conductive pads; loading the package substrate on a bottom chase with the front surface facing upward; pressing, with a top chase, the front electronic components against the bottom chase to reshape the solder bumps and horizontally align top surfaces of the front electronic components with each other; and forming a front mold cap on the front surface to encapsulate the front electronic components.

公开(公告)号：US20240332114A1

公开(公告)日：2024-10-03

申请号：US18597878

申请日：2024-03-06

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE ,  YongMoo SHIN

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/42 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L24/08 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/27 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2225/06568

Abstract: A semiconductor device is provided. The semiconductor device includes a primary semiconductor die with a top surface, wherein the top surface comprising a first region and a second region besides the first region; an auxiliary semiconductor die attached onto the first region of the top surface of the primary semiconductor die; a thermally conductive laminated structure formed on the primary semiconductor die and the auxiliary semiconductor die, wherein the thermally conductive laminated structure at least partially covers the second region of the top surface of the primary semiconductor die, and at least partially covers a top surface of the auxiliary semiconductor die; and a heat spreader thermally coupled to the primary semiconductor die and the auxiliary semiconductor die through at least the thermally conductive laminated structure.

公开(公告)号：US20240120268A1

公开(公告)日：2024-04-11

申请号：US18475255

申请日：2023-09-27

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HunTaek LEE ,  KyoungHee PARK ,  SeongHwan PARK ,  YoungHoon JEON ,  HeeSoo LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/552 ,  H01L25/162

Abstract: A method for forming a shielding layer on a semiconductor device is disclosed. The semiconductor device comprises a bond pad formed on a front side of a substrate and extends to a first lateral surface of the substrate. The method comprises: etching a portion of the bond pad adjacent to the first lateral surface, to form a gap between the bond pad and the first lateral surface; attaching a filler onto the bond pad to fill the gap; and applying a shielding layer to a back side of the substrate.

公开(公告)号：US20240057249A1

公开(公告)日：2024-02-15

申请号：US18446487

申请日：2023-08-09

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE ,  YeJin PARK

IPC: H05K1/02 ,  H05K1/18 ,  H01L25/16 ,  H01L23/31 ,  H01L23/552 ,  H05K9/00 ,  H01L21/56 ,  H05K3/28

CPC classification number: H05K1/0271 ,  H05K1/18 ,  H01L25/16 ,  H01L23/3121 ,  H01L23/552 ,  H05K9/0022 ,  H01L21/56 ,  H05K3/284 ,  H05K2201/2009 ,  H05K2201/10189 ,  H05K2203/1316 ,  H05K2203/1322

Abstract: An electronic package comprises: a substrate comprising a first region and a second region adjacent to the first region in a lengthwise direction of the substrate; a first electronic component mounted on the substrate in the first region; a second electronic component mounted on the substrate in the second region, wherein the second electronic component does not occupy an entirety of the substrate in a widthwise direction of the substrate; and an encapsulant layer formed on the substrate, wherein at least the second electronic component is exposed from the encapsulant layer, and wherein the encapsulant layer extends from the first region to the second region to reinforce the substrate in both the first region and the second region.

公开(公告)号：US20240120289A1

公开(公告)日：2024-04-11

申请号：US18475249

申请日：2023-09-27

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  YeJin PARK ,  HeeSoo LEE

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/16155 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2924/142 ,  H01L2924/1431 ,  H01L2924/182 ,  H01L2924/3025

Abstract: An electronic package is provided. The electronic package comprises a substrate having a first region and a second region; a first set of electronic components mounted on the substrate in the first region; a second set of electronic components mounted on the substrate in the second region; an encapsulant layer disposed on the substrate and encapsulating the first and second sets of electronic components; a set of interconnect components disposed on the substrate in the second region, and extending through the encapsulant layer, wherein the set of interconnect components are electrically coupled to the first and second sets of electronic components; and a connector mounted on the encapsulant layer and electrically coupled to the first and second sets of electronic components through the set of interconnect components.

公开(公告)号：US20250140679A1

公开(公告)日：2025-05-01

申请号：US18929640

申请日：2024-10-29

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SangHoon LEE ,  SeungHyun LEE ,  HeeSoo LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/66 ,  H01L25/16

Abstract: A method for forming an electronic package assembly is provided. The method comprises: providing a base package substrate, wherein the base package substrate comprises a first package substrate, a second package substrate and an interconnect portion, and wherein first and second sets of conductive patterns are both formed on a front surface of the base package substrate; attaching a flexible cable linkage onto the front surface of the base package substrate and across the interconnect portion to electrically connect the first set of conductive patterns with the second set of conductive patterns; attaching a mold chase on the front surface of the base package substrate; forming a first mold cap within the first cavity and a second mold cap within the second cavity; and removing the interconnect portion from the base package substrate.

公开(公告)号：US20240421015A1

公开(公告)日：2024-12-19

申请号：US18746135

申请日：2024-06-18

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  YeJin PARK ,  HeeSoo LEE ,  HyunSu TAK ,  SangJun PARK

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/552 ,  H01L25/16 ,  H01R12/52

Abstract: A semiconductor package is disclosed. The semiconductor package comprises: a metal shim, a package substrate attached onto a front side of the metal shim, wherein the package substrate comprises an opening that passes therethrough; one or more electronic components mounted on the package substrate; an encapsulant layer partially formed on the package substrate to expose a region of the package substrate and the opening of the package substrate, wherein the encapsulant layer encapsulates the one or more electronic components on the package substrate; a first connector mounted in the exposed region of the package substrate; a second connector mounted in the encapsulant layer and on the package substrate; and a magnet mounted in the opening of the package substrate and extending from the metal shim through the package substrate and the encapsulant layer.

公开(公告)号：US20240404911A1

公开(公告)日：2024-12-05

申请号：US18670747

申请日：2024-05-22

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE ,  YongMoo SHIN

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package includes a primary semiconductor die with a top surface, wherein the top surface comprising a first region and a second region besides the first region; an auxiliary semiconductor die attached on the first region of the top surface of the primary semiconductor die; a primary heat spreader assembly attached on the second region of the top surface of the primary semiconductor die; and an auxiliary heat spreader assembly attached on a top surface of the auxiliary semiconductor die, wherein the primary heat spreader assembly is thermally isolated from the auxiliary heat spreader assembly.

公开(公告)号：US20250140773A1

公开(公告)日：2025-05-01

申请号：US18926424

申请日：2024-10-25

Applicant: JCET STATS ChipPAC Korea Limited

Inventor： SeungHyun LEE ,  HeeSoo LEE

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/10

Abstract: A method for forming the same is provided. The method comprises: providing a package substrate; attaching back conductive blocks onto a back surface of the package substrate via back solder bump; loading the package substrate on a first bottom chase with the back conductive blocks facing upward, and pressing, with a first top chase, the back conductive blocks against the first bottom chase to reshape the back solder bumps and horizontally align top surfaces of the back conductive blocks with each other; attaching front conductive blocks onto a front surface of the package substrate via front solder bumps; loading the package substrate on a second bottom chase with the front conductive blocks facing upward, and pressing, with a second top chase, the front conductive blocks against the second bottom chase to reshape the front solder bumps and horizontally align top surfaces of the front conductive blocks with each other.