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    Multilayer substrate
    3.
    发明授权
    Multilayer substrate 有权
    多层基板

    公开(公告)号：US09532469B2

    公开(公告)日：2016-12-27

    申请号：US14317498

    申请日：2014-06-27

    Applicant: FUJITSU LIMITED

    Inventor： Shunji Baba ,  Takashi Kanda

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K1/14

    CPC classification number: H05K3/4694 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/14 ,  H05K2201/0352 ,  H05K2203/061

    Abstract: A multilayer substrate includes a first substrate a second substrate that is stacked on and electrically connected to the first substrate, the second substrate having a different characteristic from a characteristic of the first substrate, a third substrate that is provided on a side of the first substrate, the second substrate being provided on the side of the first substrate, and the third substrate is electrically connected to the second substrate, and a connection member that electrically connects the first substrate and the third substrate to each other while the second substrate is bypassed.

    Abstract translation: 多层基板包括第一基板和第二基板，第二基板层叠并电连接到第一基板，第二基板具有与第一基板的特性不同的特性，第三基板设置在第一基板的一侧 所述第二基板设置在所述第一基板的一侧，并且所述第三基板电连接到所述第二基板，以及连接构件，其在所述第二基板旁路的同时使所述第一基板和所述第三基板彼此电连接。

    Rough Copper for Noise Reduction in High Speed Circuits
    4.
    发明申请
    Rough Copper for Noise Reduction in High Speed Circuits 审中-公开
    粗铜在高速电路中降噪

    公开(公告)号：US20160088722A1

    公开(公告)日：2016-03-24

    申请号：US14492867

    申请日：2014-09-22

    Applicant: Dell Products, LP

    Inventor： Sandor Farkas ,  Bhyrav M. Mutnury

    IPC: H05K1/02 ,  H05K1/09 ,  C25D5/02 ,  H05K3/18 ,  C25D7/00

    CPC classification number: C25D5/02 ,  H05K1/0242 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2203/0307

    Abstract: A method includes providing, on a printed circuit board, a first copper layer having a first surface roughness, forming, by the first copper layer a power trace to a circuit device, providing, on the printed circuit board, a second copper layer having a second surface roughness, wherein the first surface roughness is greater than the second surface roughness, and forming, by the second copper layer, a signal trace to the circuit device.

    Abstract translation: 一种方法包括在印刷电路板上提供具有第一表面粗糙度的第一铜层，通过第一铜层将电源轨迹形成电路装置，在印刷电路板上提供第二铜层，第二铜层具有 第二表面粗糙度，其中第一表面粗糙度大于第二表面粗糙度，并且由第二铜层形成到电路器件的信号迹线。

    ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREFOR
    8.
    发明申请
    ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREFOR 有权
    电子元件及其制造方法

    公开(公告)号：US20150156868A1

    公开(公告)日：2015-06-04

    申请号：US14611513

    申请日：2015-02-02

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Masato NOMIYA

    IPC: H05K1/02 ,  H05K3/00 ,  H05K3/12 ,  H05K1/03

    CPC classification number: H05K1/0298 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K3/0067 ,  H05K3/12 ,  H05K3/4629 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09336 ,  H05K2201/09736

    Abstract: The electronic component of this invention includes a multilayer ceramic substrate 14 composed of a plurality of ceramic layers 12. A wiring electrode 16 and a planar electrode 18 are formed on a ceramic layer 12, which is an insulating layer. The planar electrode 18 is formed so as to be spaced apart from the wiring electrode 16 at the certain interval. An edge portion 22 is formed in a region of the planar electrode 18 adjacent to and spaced apart from the wiring electrode 16 at a certain interval. A central portion 20 is formed in a region of the planar electrode 18 other than the edge portion 22. At least the composition of the central portion 20 is different from the composition of the wiring electrode 16, and the composition of the edge portion 22 is the same as the composition of the wiring electrode 16.

    Abstract translation: 本发明的电子部件包括由多个陶瓷层12构成的多层陶瓷基板14.在作为绝缘层的陶瓷层12上形成有布线电极16和平面电极18。 平面电极18形成为以一定间隔与布线电极16间隔开。 边缘部分22以一定间隔形成在平面电极18的与布线电极16相邻并间隔开的区域中。 中心部分20形成在平面电极18的除了边缘部分22的区域中。至少中心部分20的组成与布线电极16的组成不同，边缘部分22的组成是 与布线电极16的组成相同。

    PRINTED CIRCUIT BOARD AND MANUFACTURE METHOD THEREOF
    10.
    发明申请
    PRINTED CIRCUIT BOARD AND MANUFACTURE METHOD THEREOF 审中-公开
    印刷电路板及其制造方法

    公开(公告)号：US20150021074A1

    公开(公告)日：2015-01-22

    申请号：US14298098

    申请日：2014-06-06

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Sang Hoon KIM ,  Tae Hong MIN ,  Jung Han LEE ,  Hye Jin KIM

    IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/00 ,  H05K3/30

    CPC classification number: H05K1/0271 ,  H01L2924/3511 ,  H05K1/111 ,  H05K1/115 ,  H05K1/185 ,  H05K3/0097 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09136 ,  H05K2203/0191 ,  H05K2203/1536 ,  Y10T29/49139

    Abstract: Disclosed herein is a printed circuit board capable of implementing slimness by decreasing the number of entire layers through an asymmetrical build-up structure in which an electric device is embedded, the printed circuit board including: a core layer including a cavity formed therein so that an electric device is embedded and a circuit pattern and a pad formed on upper and lower surfaces thereof; a through via formed in the core layer so as to connect the upper and the lower pads of the core layer to each other; a plurality of insulating layers built-up on the core layer and including a plurality of vias so as to be electrically connected to the through via; and a solder resist layer applied onto a lower portion of the core layer so that a lower surface of the through via is partially exposed.

    Abstract translation: 本发明公开了一种印刷电路板，其能够通过使嵌入电气装置的不对称积聚结构减少整个层数来实现薄片化，该印刷电路板包括：芯层，其包括形成在其中的空腔， 电气装置被嵌入，并且在其上表面和下表面上形成电路图案和焊盘; 通孔形成在芯层中，以将芯层的上垫和下焊盘彼此连接; 多个绝缘层，其堆叠在所述芯层上并且包括多个通孔，以便电连接到所述通孔; 以及涂覆在芯层的下部上的阻焊层，使得通孔的下表面部分露出。

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