公开(公告)号：US09679652B2

公开(公告)日：2017-06-13

申请号：US14702770

申请日：2015-05-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hiroshi Watanabe

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value. Accordingly, the reliability of the first memory cell may be improved.

公开(公告)号：US20170154656A1

公开(公告)日：2017-06-01

申请号：US14997575

申请日：2016-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G11C7/00 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C7/00 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C5/005 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/345 ,  G11C29/42 ,  G11C29/52

Abstract: A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.

公开(公告)号：US20170147216A1

公开(公告)日：2017-05-25

申请号：US15000021

申请日：2016-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chun-Yang Hu

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7205

Abstract: A method and a system for memory management and a memory storage device thereof are provided. The memory storage device includes a rewritable non-volatile memory module. The method includes receiving a command from a host system; reading use information from the rewritable non-volatile memory module according to the command; writing the use information into a first physical erasing unit of the rewritable non-volatile memory module, and marking the first physical erasing unit with a recognizing flag. The method also includes erasing data in at least part of physical erasing units excepting the first physical erasing unit in the rewritable non-volatile memory module according to the recognizing flag; and establishing a memory management table according to the use information stored in the first physical erasing unit for operating the memory storage device.

公开(公告)号：US09652378B2

公开(公告)日：2017-05-16

申请号：US13950284

申请日：2013-07-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Hwa Ho ,  Kheng-Chong Tan

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: A writing method, a memory controller and a memory storage device are provided. The writing method includes steps of: configuring logical addresses to map to part of physical programming units in a storage area, wherein at least one of the physical programming units stores a valid data; transmitting a first write command for writing data having a first data length to at least one of the physical programming units; receiving a status signal; and selecting a spare physical erasing unit and copying the valid data having a second data length to the spare physical erasing unit, after transmitting the first write command and before receiving the status signal, wherein the first data length is not greater than the second data length. Therefore, it prevents a host system from waiting too long when writing data.

公开(公告)号：US09619380B2

公开(公告)日：2017-04-11

申请号：US14038780

申请日：2013-09-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A data writing method for a memory storage apparatus having a first buffer memory, a second buffer memory and a rewritable non-volatile memory module is provided, and the transmission bandwidth of the first buffer memory is larger than the transmission bandwidth of the second buffer memory. The method includes: receiving a write command and first data thereof; determining whether the first data belongs to the successive big data; if the first data belongs to the successive big data, temporarily storing the first data into a first data buffer area of the first buffer memory, writing the first write data from the first data buffer area to the rewritable non-volatile memory module; and if the first data does not belongs to the successive big data, temporarily storing the first data into a second data buffer area of the second buffer memory.

公开(公告)号：US09613707B1

公开(公告)日：2017-04-04

申请号：US15080595

申请日：2016-03-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chia-Yi Chen

IPC: G11C16/14 ,  G11C16/34

CPC classification number: G11C16/14 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C2211/5641

Abstract: A data programming method includes setting a plurality of first type physical erasing units as a current writing area and recording a current writing data amount. The method also includes calculating a data amount threshold according to the first type physical erasing units. The method still includes receiving data. The method further includes: if the current writing data amount is less than the data amount threshold, programming the data to at least one of the first type physical erasing units using a first programming mode; and if the current writing data amount is not less than the data amount threshold, setting a plurality of second type physical erasing units as the current writing area and programming the data to at least one physical erasing unit of the second type physical erasing units using a second programming mode.

公开(公告)号：US09612630B2

公开(公告)日：2017-04-04

申请号：US14742664

申请日：2015-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Hung Lin

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  G06F1/18

CPC classification number: G06F1/181 ,  G06K19/07732 ,  H05K5/0278

Abstract: A flash drive including a housing, a carrier, and a storage module is provided. The carrier is movably disposed inside the housing along a first axis. The carrier has an elastic arm being deformable along a second axis. The storage module is assembled to the carrier to move together with the carrier in relative to the housing, so that a connector of the storage module is moved outside the housing or hidden inside the housing. The elastic arm has a contour protruded along a direction away from the storage module when not receiving force.

公开(公告)号：US09583217B2

公开(公告)日：2017-02-28

申请号：US14296383

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G11C29/00 ,  G11C29/52 ,  H03M13/37 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/3746

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元，该解码方法包括：根据硬判定电压读取多个存储单元以获得硬比特; 对所述硬比特执行奇偶校验处理以获得多个综合征; 根据综合征确定硬比特是否有错误; 如果硬比特错误，则根据与硬比特相对应的硬比特和综合征权重信息的信道信息更新硬比特。

公开(公告)号：US20170052720A1

公开(公告)日：2017-02-23

申请号：US14887332

申请日：2015-10-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Hua Chu

IPC: G06F3/06

CPC classification number: G11C16/22 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0646 ,  G11C16/225 ,  G11C16/32 ,  G11C16/3418

Abstract: A data protection method for a memory storage apparatus is provided. The method includes obtaining a current system time from a host system as a boot time, if the memory storage apparatus is powered on, and a basic input/output system of the host system loads and executes instruction programs in the expansion ROM of the memory storage apparatus for transmitting the current system time to the memory storage apparatus. The method also includes obtaining a shutdown time corresponding to the memory storage apparatus; calculating an off time from the shutdown time to the boot time and performing a refresh operation on physical erasing units of a rewritable non-volatile memory in the memory storage apparatus if the off time is longer than an off time threshold.

Abstract translation: 提供了一种用于存储器装置的数据保护方法。 该方法包括：如果存储器存储设备通电，则从主机系统获取当前系统时间作为引导时间，并且主机系统的基本输入/输出系统在存储器存储器的扩展ROM中加载并执行指令程序 用于将当前系统时间发送到存储器存储装置的装置。 该方法还包括获得对应于存储器存储装置的关机时间; 计算从关机时间到引导时间的关闭时间，并且如果关闭时间长于关闭时间阈值，则对存储器存储装置中的可重写非易失性存储器的物理擦除单元执行刷新操作。

公开(公告)号：US20170038977A1

公开(公告)日：2017-02-09

申请号：US14872154

申请日：2015-10-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: selecting a first physical erasing unit, and loading a first logical address-physical address mapping table according to a physical address-logical address mapping table. The method also includes: updating the first logical address-physical address mapping table according to the physical address-logical address mapping table, and identifying valid data in the first physical erasing unit according to the physical address-logical address mapping table and the first logical address-physical address mapping table. The method further includes: storing the first logical address-physical address mapping table, copying the valid data to a second physical erasing unit, and performing an erasing operation for the first physical erasing unit.

Abstract translation: 提供有效的数据合并方法，存储器控制器和存储器存储装置。 该方法包括：选择第一物理擦除单元，并根据物理地址 - 逻辑地址映射表加载第一逻辑地址 - 物理地址映射表。 该方法还包括：根据物理地址 - 逻辑地址映射表更新第一逻辑地址 - 物理地址映射表，并根据物理地址 - 逻辑地址映射表和第一逻辑地址映射表识别第一物理擦除单元中的有效数据 地址 - 物理地址映射表。 该方法还包括：存储第一逻辑地址 - 物理地址映射表，将有效数据复制到第二物理擦除单元，以及对第一物理擦除单元执行擦除操作。