公开(公告)号：US10854541B2

公开(公告)日：2020-12-01

申请号：US16554008

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L27/082 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20190385780A1

公开(公告)日：2019-12-19

申请号：US16012259

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01L21/822 ,  H01L23/522 ,  H01L49/02 ,  H01F41/04

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US10403564B2

公开(公告)日：2019-09-03

申请号：US15859332

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Hiroki Tanaka ,  Robert A. May ,  Kristof Darmawikarta ,  Changhua Liu ,  Chung Kwang Tan ,  Srinivas Pietambaram ,  Sri Ranga Sai Boyapati

IPC: H01L21/027 ,  H01L21/48 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20190250326A1

公开(公告)日：2019-08-15

申请号：US16061540

申请日：2015-12-14

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Darmawikarta ,  Rahul Jain ,  Sri Ranga Sai Boyapati ,  Maroun Moussallem ,  Rahul N. Manepalli ,  Srinivas Pietambaram

IPC: G02B6/122 ,  G02B6/132 ,  H01P5/107

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/134 ,  G02B2006/12035 ,  H01P5/107

Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.

公开(公告)号：US20180376585A1

公开(公告)日：2018-12-27

申请号：US15780327

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Javier Soto Gonzalea ,  Meizi Jiao ,  Shruti R. Jaywant ,  Oscar Ojeda ,  Sashi S. Kandanur ,  Srinivas Pietambaram ,  Roy Dittler ,  Rajat Goyal ,  Dilan Seneviratne

IPC: H05K1/02 ,  H05K3/06 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K3/30

CPC classification number: H05K1/0283 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H05K1/115 ,  H05K1/189 ,  H05K3/064 ,  H05K3/284 ,  H05K3/303 ,  H05K3/4053 ,  H05K3/4682 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/043

Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.

公开(公告)号：US20180295720A1

公开(公告)日：2018-10-11

申请号：US15762791

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Javier Soto Gonzalez ,  Dilan Seneviratne ,  Shruti R. Jaywant ,  Sashi S. Kandanur ,  Srinivas Pietambaram ,  Nadine L. Dabby ,  Braxton Lathrop ,  Rajat Goyal ,  Vivek Raghunathan

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/18 ,  H05K3/46 ,  H05K3/00 ,  H05K3/34 ,  H05K3/28 ,  H05K3/42

CPC classification number: H05K1/0283 ,  H01L23/145 ,  H01L23/5387 ,  H05K1/038 ,  H05K1/111 ,  H05K1/189 ,  H05K3/0023 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/0055 ,  H05K3/18 ,  H05K3/205 ,  H05K3/284 ,  H05K3/341 ,  H05K3/429 ,  H05K3/4661 ,  H05K3/4682 ,  H05K2201/0133 ,  H05K2201/0329 ,  H05K2201/09263 ,  H05K2201/10098 ,  H05K2201/10151 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body.

公开(公告)号：US20170142839A1

公开(公告)日：2017-05-18

申请号：US14943234

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Srinivas Pietambaram ,  Rahul N. Manepalli

IPC: H05K1/18 ,  H05K3/46 ,  H05K3/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/184 ,  H01L2224/04105 ,  H01L2924/18162 ,  H05K1/0283 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/185 ,  H05K3/007 ,  H05K3/4697 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/0191 ,  H05K2203/1469

Abstract: An embedded electronic package includes a stretchable body that includes at least one electronic component, wherein each electronic component includes a back side that is exposed from the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components. In some forms, the embedded electronic package includes a stretchable body that includes an upper surface and a lower surface, wherein the stretchable body includes at least one electronic component, wherein each electronic component is fully embedded in the stretchable body and the same distance from the upper surface of the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components.

公开(公告)号：US20250112162A1

公开(公告)日：2025-04-03

申请号：US18375469

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Zheng Kang ,  Tchefor Ndukum ,  Yosuke Kanaoka ,  Jeremy Ecton ,  Gang Duan ,  Jefferson Kaplan ,  Yonggang Yong Li ,  Minglu Liu ,  Brandon C. Marin ,  Bai Nie ,  Srinivas Pietambaram ,  Shriya Seshadri ,  Bohan Shan ,  Deniz Turan ,  Vishal Bhimrao Zade

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.

公开(公告)号：US20250112161A1

公开(公告)日：2025-04-03

申请号：US18478538

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Minglu Liu ,  Seyyed Yahya Mousavi ,  Yingying Zhang ,  Gang Duan ,  Andrey Gunawan ,  Yosuke Kanaoka ,  Yiqun Bai ,  Ziyin Lin ,  Bohan Shan ,  Dingying Xu ,  Srinivas Pietambaram ,  Hong Seung Yeon

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.

公开(公告)号：US20250112124A1

公开(公告)日：2025-04-03

申请号：US18374555

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Leonel Arana ,  Gang Duan ,  Benjamin Duong ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon C. Marin ,  Tchefor Ndukum ,  Bai Nie ,  Srinivas Pietambaram ,  Bohan Shan ,  Matthew Tingey

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and below the IC die; and a gap within the dielectric material and extending around the metallization pattern.