公开(公告)号：US11127664B2

公开(公告)日：2021-09-21

申请号：US15391861

申请日：2016-12-28

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Kai-Ming Yang ,  Wang-Hsiang Tsai ,  Tzyy-Jang Tseng

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K3/46 ,  H01L23/14 ,  H01L23/15

Abstract: A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.

公开(公告)号：US20210247147A1

公开(公告)日：2021-08-12

申请号：US17168200

申请日：2021-02-05

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: F28D15/04 ,  F28D15/02 ,  F28F21/08 ,  F28F3/10 ,  B23P15/26

Abstract: A vapor chamber structure including a thermally conductive shell, a capillary structure layer, and a working fluid is provided. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion has at least one first cavity. The second thermally conductive portion and the first cavity define at least one sealed chamber, and a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.

公开(公告)号：US10897823B2

公开(公告)日：2021-01-19

申请号：US16361180

申请日：2019-03-21

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Chih-Lun Wang

IPC: H05K1/18 ,  H05K1/09 ,  H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46

Abstract: A circuit board including an interconnect substrate and a multilayer structure is provided. The interconnect substrate includes a core layer and a conductive structure disposed on the core layer. The multilayer structure is disposed on the conductive structure. The multilayer structure includes a plurality of dielectric layers and a plurality of circuit structures. The circuit structures are disposed in the dielectric layers. A topmost layer in the circuit structures is exposed to the dielectric layers to be in contact with the conductive structure. A pattern of the topmost layer in the circuit structures and a pattern of a top surface of the conductive structure are engaged with each other.

公开(公告)号：US10863618B2

公开(公告)日：2020-12-08

申请号：US16283670

申请日：2019-02-22

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Pei-Wei Wang ,  Bo-Cheng Lin ,  Chun-Hsien Chien ,  Chien-Chou Chen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/30 ,  H05K3/46 ,  H01Q3/38 ,  H01Q1/24 ,  H01Q1/38 ,  H05K3/02 ,  H05K3/40 ,  H05K1/18

Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.

公开(公告)号：US10756050B2

公开(公告)日：2020-08-25

申请号：US16152424

申请日：2018-10-05

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen

IPC: H01L29/40 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package structure is also provided.

公开(公告)号：US09859130B2

公开(公告)日：2018-01-02

申请号：US14568084

申请日：2014-12-11

Applicant: Unimicron Technology Corp.

Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

IPC: H01L21/48 ,  H05K1/11 ,  H05K3/46 ,  C25D1/00 ,  H05K3/42

CPC classification number: H01L21/481 ,  C25D1/003 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T156/10

Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

公开(公告)号：US20170025342A1

公开(公告)日：2017-01-26

申请号：US15287729

申请日：2016-10-06

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Yu-Hua Chen ,  Ra-Min Tain

IPC: H01L23/498 ,  H01L23/48 ,  C25D7/12 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/49833 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  C25D7/123 ,  H01L21/486 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.

Abstract translation: 提供了包括模制化合物，载体板，芯片，多个导电柱和电路板的芯片封装结构。 载体板包括基板和再分布层。 基板具有第一表面和第二表面。 再分配层设置在第一表面上。 芯片和导电柱设置在再分配层上。 模塑料覆盖芯片，导电柱和再分布层。 电路板与承载板连接，其中电路板设置在模塑料上，使得芯片位于基板和电路板之间，并且芯片和再分布层通过电路板电连接 导电支柱。 由芯片产生的热量通过基板从第一表面传递到第二表面以消散。

公开(公告)号：US09370107B2

公开(公告)日：2016-06-14

申请号：US14255971

申请日：2014-04-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Wei-Ming Cheng

IPC: H05K13/04 ,  H05K1/18 ,  H05K3/28 ,  H05K1/11 ,  H01L27/00

CPC classification number: H05K13/04 ,  H05K1/11 ,  H05K1/114 ,  H05K1/183 ,  H05K1/184 ,  H05K1/186 ,  H05K3/284 ,  H05K2201/09072 ,  H05K2201/10083 ,  H05K2201/10121 ,  H05K2201/10151

Abstract: An embedded component structure includes a wiring board, a component and an encapsulant. The wiring board has a front side, a reverse side opposite to the front side, an opening and an interconnection layer. The opening penetrates the wiring board and connects the front side and the reverse side of the wiring board. The interconnection layer is located on the front side of the wiring board and extends toward the opening. The component includes an active surface, a back side opposite to the active side, and a working area located on the active surface. The active surface is connected to the interconnection layer of the wiring board. The encapsulant is filled inside the opening and covers the component, which makes the working area of the component exposed. Besides, a method of the embedded component structure is also provided.

Abstract translation: 嵌入式组件结构包括布线板，部件和密封剂。 布线板具有前侧，与前侧相反的反面，开口和互连层。 开口穿过布线板并连接布线板的正面和背面。 互连层位于布线板的正面，朝向开口部延伸。 该部件包括活动表面，与活动侧相对的后侧以及位于活动表面上的工作区域。 有源表面连接到布线板的互连层。 密封剂填充在开口内部并覆盖部件，这使得部件的工作区域暴露。 此外，还提供了嵌入式组件结构的方法。

公开(公告)号：US09282646B2

公开(公告)日：2016-03-08

申请号：US14164245

申请日：2014-01-26

Applicant: Unimicron Technology Corp.

Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

IPC: H05K1/11 ,  H05K3/10 ,  C25D1/00 ,  H05K3/46 ,  H05K3/42

CPC classification number: H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。

公开(公告)号：US20140174804A1

公开(公告)日：2014-06-26

申请号：US13726230

申请日：2012-12-24

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K3/007 ,  H01L23/5389 ,  H01L24/19 ,  H01L2924/12042 ,  H05K1/18 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0011 ,  H05K3/06 ,  H05K3/30 ,  H05K3/423 ,  H05K3/465 ,  H05K2203/0723 ,  H05K2203/1469 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.

Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中通过第一导电图案在电介质层中形成第一凹陷图案。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。 此外，还提供了电气装置封装结构。