公开(公告)号：US20200144100A1

公开(公告)日：2020-05-07

申请号：US16733214

申请日：2020-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure on a fin-shaped structure, a single diffusion break (SDB) structure adjacent to the gate structure, a shallow trench isolation (STI) around the fin-shaped structure, and an isolation structure on the STI. Preferably, a top surface of the SDB structure is even with a top surface of the isolation structure, and the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion.

公开(公告)号：US20190296124A1

公开(公告)日：2019-09-26

申请号：US15951147

申请日：2018-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.

公开(公告)号：US20190206672A1

公开(公告)日：2019-07-04

申请号：US16273003

申请日：2019-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/67 ,  H01L29/165 ,  H01L27/088 ,  H01L29/78 ,  H01L21/762 ,  H01L29/49

Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.

公开(公告)号：US20150108587A1

公开(公告)日：2015-04-23

申请号：US14057095

申请日：2013-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chen ,  Chung-Hsien Tsai ,  Tung-Ming Chen ,  Chih-Sheng Chang ,  Jun-Chi Huang ,  Chih-Jen Lin ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/28052 ,  H01L21/2652 ,  H01L21/28114 ,  H01L29/42372 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7847

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.

Abstract translation: 提供半导体结构及其形成方法。 该方法包括以下步骤。 在基板上形成栅极电极层。 间隔结构形成在栅电极层的侧壁上。 形成介电盖膜以覆盖栅电极层和间隔结构。 在介质盖膜暴露于源极/漏极注入的条件下，对衬底进行源极/漏极注入。

公开(公告)号：US20250151320A1

公开(公告)日：2025-05-08

申请号：US18531668

申请日：2023-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi Chuen Eng ,  Tzu-Feng Chang ,  Teng-Chuan Hu ,  Yi-Wen Chen ,  Yu-Hsiang Lin

IPC: H01L29/78

Abstract: A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.

公开(公告)号：US12272693B2

公开(公告)日：2025-04-08

申请号：US17700475

申请日：2022-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

公开(公告)号：US12243839B2

公开(公告)日：2025-03-04

申请号：US18430670

申请日：2024-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Sung Chiang ,  Chia-Wei Liu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/488 ,  H01L23/532 ,  H01L25/065

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.

公开(公告)号：US12211915B2

公开(公告)日：2025-01-28

申请号：US18115780

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US12211751B2

公开(公告)日：2025-01-28

申请号：US18398190

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US20240347588A1

公开(公告)日：2024-10-17

申请号：US18196441

申请日：2023-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Po-Kuang Hsieh ,  Jia-He Lin ,  Sheng-Yao Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.