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    MEMS device, liquid ejecting head, and liquid ejecting apparatus
    92.
    发明授权
    MEMS device, liquid ejecting head, and liquid ejecting apparatus 有权

    公开(公告)号：US09770907B2

    公开(公告)日：2017-09-26

    申请号：US15354851

    申请日：2016-11-17

    Applicant: SEIKO EPSON CORPORATION

    Inventor： Katsutomo Tsukahara ,  Motoki Takabe ,  Eiju Hirai ,  Masao Nakayama ,  Munehide Saimen

    IPC: B41J2/045 ,  B41J2/14 ,  B81B7/00

    CPC classification number: B41J2/14201 ,  B41J2/14233 ,  B41J2002/14241 ,  B41J2002/14266 ,  B41J2002/14491 ,  B41J2202/11 ,  B41J2202/18 ,  B81B7/0061 ,  B81B2201/052

    Abstract: A MEMS device includes a drive region having a stacked structural body in which a first electrode layer, a first dielectric layer, and a second electrode layer are stacked in that order. The stacked structural body extends from the drive region to a non-drive region that is outer than the drive region and, in an extending direction of the stacked structural body, the first electrode layer and the first dielectric layer extend farther outward than the second electrode layer. A second dielectric layer covering an end of the second electrode layer in the extending direction is stacked on the second electrode layer in the non-drive region and the first dielectric layer that is formed outer in the extending direction than the second electrode layer. A third electrode layer electrically connected to the second electrode layer is stacked on the second dielectric layer and on the second electrode layer in a region outside the second dielectric layer. In the extending direction, the end of the second electrode layer is formed more to a drive region side than a second dielectric layer-side end of the third electrode layer.

    Process for filling etched holes
    93.
    发明授权
    Process for filling etched holes 有权

    公开(公告)号：US09708183B2

    公开(公告)日：2017-07-18

    申请号：US15046239

    申请日：2016-02-17

    Applicant: Memjet Technology Ltd.

    Inventor： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

    IPC: B81C1/00 ,  B41J2/16

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

    HEATING SYSTEM AND METHOD FOR MICROFLUIDIC AND MICROMECHANICAL APPLICATIONS
    94.
    发明申请
    HEATING SYSTEM AND METHOD FOR MICROFLUIDIC AND MICROMECHANICAL APPLICATIONS 审中-公开
    微流体和微生物应用的加热系统和方法

    公开(公告)号：US20160347610A1

    公开(公告)日：2016-12-01

    申请号：US15234312

    申请日：2016-08-11

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Ming FANG ,  Fuchao WANG

    IPC: B81C1/00 ,  H01L49/02 ,  B81B1/00

    CPC classification number: B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/49401 ,  Y10T29/49826

    Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

    Abstract translation: 集成半导体加热组件包括半导体衬底，形成在其中的室和与室流体连通的出口，使得流体响应于加热室而离开室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。

    PROCESS FOR FILLING ETCHED HOLES
    96.
    发明申请
    PROCESS FOR FILLING ETCHED HOLES 有权
    填充蚀刻孔的方法

    公开(公告)号：US20160236930A1

    公开(公告)日：2016-08-18

    申请号：US15046239

    申请日：2016-02-17

    Applicant: Memjet Technology Ltd.

    Inventor： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

    IPC: B81C1/00

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

    Abstract translation: 一种用于填充限定在晶片衬底的前表面中的一个或多个蚀刻孔的工艺。 该方法包括以下步骤：（i）将热塑性第一聚合物层沉积到前表面和每个孔中; （ii）回流第一聚合物; （iii）将晶片衬底暴露于受控氧化等离子体; （iv）任选地重复步骤（i）至（iii）; （v）沉积可光成像的第二聚合物层; （vi）使用曝光和显影从所述孔的外周边区域选择性地除去所述第二聚合物; 和（vii）平面化前侧表面以提供填充有彼此不同的第一和第二聚合物的塞子的孔。 每个插头具有与前侧表面共面的相应的上表面。

    HEATING SYSTEM AND METHOD FOR MICROFLUIDIC AND MICROMECHANICAL APPLICATIONS
    98.
    发明申请
    HEATING SYSTEM AND METHOD FOR MICROFLUIDIC AND MICROMECHANICAL APPLICATIONS 审中-公开
    微流体和微生物应用的加热系统和方法

    公开(公告)号：US20140304990A1

    公开(公告)日：2014-10-16

    申请号：US14316487

    申请日：2014-06-26

    Applicant: STMicroelectronics, Inc.

    Inventor： Ming Fang ,  Fuchao Wang

    IPC: B41J2/16

    CPC classification number: B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

    Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

    Abstract translation: 集成半导体加热组件包括半导体衬底，形成在其中的腔室以及与腔室流体连通的出口，允许流体响应于加热室而离开腔室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。

    Corrugated membrane MEMS actuator fabrication method
    99.
    发明授权
    Corrugated membrane MEMS actuator fabrication method 有权
    波纹膜MEMS致动器制造方法

    公开(公告)号：US08835195B2

    公开(公告)日：2014-09-16

    申请号：US13552721

    申请日：2012-07-19

    Applicant: Yonglin Xie ,  Weibin Zhang

    Inventor： Yonglin Xie ,  Weibin Zhang

    IPC: H01L21/00

    CPC classification number: B41J2/1601 ,  B41J2/1607 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/032 ,  B81B2201/052 ,  B81C1/00158

    Abstract: A MEMS device fabrication method includes providing a substrate and a chamber wall material layer on a first surface of the substrate, the chamber wall material layer including a chamber cavity having a sacrificial material located therein. A mask material is deposited on the chamber wall material layer and the sacrificial material and patterned to form a mask pattern including a plurality of discrete portions. The mask material and some of the sacrificial material are removed to transfer the mask pattern including the plurality of discrete portions to the sacrificial material. A membrane material layer is deposited on the chamber wall material layer and the sacrificial material that includes the transferred mask pattern including the plurality of discrete portions. Some of the substrate and the sacrificial material are removed to release the membrane material layer using at least one process initiated from a second surface of the substrate.

    Abstract translation: MEMS器件制造方法包括在衬底的第一表面上提供衬底和室壁材料层，室壁材料层包括具有位于其中的牺牲材料的腔室腔。 掩模材料沉积在室壁材料层和牺牲材料上并被图案化以形成包括多个离散部分的掩模图案。 去除掩模材料和一些牺牲材料以将包括多个离散部分的掩模图案转移到牺牲材料。 膜材料层沉积在室壁材料层和牺牲材料上，该牺牲材料包括包含多个离散部分的转印掩模图案。 使用从衬底的第二表面引发的至少一种工艺，去除一些衬底和牺牲材料以释放膜材料层。

    Method of Fabricating Integrated Circuits
    100.
    发明申请
    Method of Fabricating Integrated Circuits 审中-公开
    制造集成电路的方法

    公开(公告)号：US20130095638A1

    公开(公告)日：2013-04-18

    申请号：US13653285

    申请日：2012-10-16

    Applicant: Andrew Leon Vella ,  David McLeod Johnstone ,  Kia Silverbrook

    Inventor： Andrew Leon Vella ,  David McLeod Johnstone ,  Kia Silverbrook

    IPC: H01L21/306

    CPC classification number: H01L21/306 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1645 ,  B81B2201/052 ,  B81C1/00476 ,  B81C2201/0108

    Abstract: A method of fabricating integrated circuits is provided in which sacrificial material is provided on a first surface of a substrate to define structural elements, integrated circuit material is provided on the sacrificial material to provide integrated circuit structures as defined by the structural elements, the sacrificial material is removed from the first surface of the substrate to provide partially fabricated integrated circuits defined by the integrated circuit structures, a carrier handle is attached to the partially fabricated integrated circuits, and the substrate is thinned from a second surface of the substrate opposite the first surface to provide the fabricated integrated circuits.

    Abstract translation: 提供一种制造集成电路的方法，其中牺牲材料设置在基板的第一表面上以限定结构元件，在牺牲材料上提供集成电路材料，以提供由结构元件限定的集成电路结构，牺牲材料 从衬底的第一表面移除以提供由集成电路结构限定的部分制造的集成电路，载体手柄附接到部分制造的集成电路，并且衬底从衬底的与第一表面相对的第二表面变薄 提供制造的集成电路。

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